From c3d1bdd0a9abcdcaee9b2246b20f7b3175c06c82 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Fri, 26 Aug 2005 21:51:29 +0000 Subject: [PATCH] teach getClass what a condition reg is llvm-svn: 23105 --- llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp index 282f1e456762..a296d32866f6 100644 --- a/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp @@ -44,10 +44,12 @@ PPC32RegisterInfo::PPC32RegisterInfo() } static const TargetRegisterClass *getClass(unsigned SrcReg) { + if (PPC32::GPRCRegisterClass->contains(SrcReg)) + return PPC32::GPRCRegisterClass; if (PPC32::FPRCRegisterClass->contains(SrcReg)) return PPC32::FPRCRegisterClass; - assert(PPC32::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR"); - return PPC32::GPRCRegisterClass; + assert(PPC32::CRRCRegisterClass->contains(SrcReg) &&"Reg not FPR, GPR, CRRC"); + return PPC32::CRRCRegisterClass; } static unsigned getIdx(const TargetRegisterClass *RC) { @@ -101,7 +103,7 @@ PPC32RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, static const unsigned Opcode[] = { PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD }; - const TargetRegisterClass *RegClass = getClass(SrcReg); + const TargetRegisterClass *RegClass = getClass(DestReg); unsigned OC = Opcode[getIdx(RegClass)]; if (DestReg == PPC::LR) { addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);