AMDGPU: Add encoding for carryless add/sub instructions
llvm-svn: 308639
This commit is contained in:
Matt Arsenault
parent
f65c5ac9c9
commit
c37fe66ec5
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@ -79,6 +79,12 @@ def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
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"Have scratch_* flat memory instructions"
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>;
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def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
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"AddNoCarryInsts",
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"true",
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"Have VALU add/sub instructions without carry out"
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>;
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def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
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"UnalignedBufferAccess",
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"true",
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@ -464,7 +470,8 @@ def FeatureGFX9 : SubtargetFeatureGeneration<"GFX9",
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FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
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FeatureFastFMAF32, FeatureDPP,
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FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
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FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts
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FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
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FeatureAddNoCarryInsts
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]
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>;
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@ -681,6 +688,12 @@ def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
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def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
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AssemblerPredicate<"FeatureFlatGlobalInsts">;
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def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarryInsts()">,
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AssemblerPredicate<"FeatureAddNoCarryInsts">;
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def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarryInsts()">,
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AssemblerPredicate<"!FeatureAddNoCarryInsts">;
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def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
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AssemblerPredicate<"Feature16BitInsts">;
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def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
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@ -167,6 +167,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
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FlatInstOffsets(false),
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FlatGlobalInsts(false),
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FlatScratchInsts(false),
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AddNoCarryInsts(false),
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R600ALUInst(false),
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CaymanISA(false),
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@ -159,6 +159,7 @@ protected:
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bool FlatInstOffsets;
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bool FlatGlobalInsts;
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bool FlatScratchInsts;
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bool AddNoCarryInsts;
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bool R600ALUInst;
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bool CaymanISA;
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bool CFALUBug;
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@ -419,6 +420,10 @@ public:
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return FlatScratchInsts;
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}
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bool hasAddNoCarry() const {
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return AddNoCarryInsts;
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}
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bool isMesaKernel(const MachineFunction &MF) const {
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return isMesa3DOS() && !AMDGPU::isShader(MF.getFunction()->getCallingConv());
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}
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@ -1300,8 +1300,43 @@ def : IntMed3Pat<V_MED3_U16, umax, umax_oneuse, umin_oneuse, i16>;
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// Assembler aliases
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//============================================================================//
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multiclass NoCarryAlias<string Inst,
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Instruction Inst32NC, Instruction Inst64NC,
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Instruction Inst32CO, Instruction Inst64CO> {
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def : InstAlias<Inst#" $vdst, $src0, $src1",
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(Inst32NC VGPR_32:$vdst, VSrc_b32:$src0, VGPR_32:$src1), 1000>,
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Requires<[HasAddNoCarryInsts]>;
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def : InstAlias<Inst#" $vdst, $src0, $src1",
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(Inst64NC VGPR_32:$vdst, VCSrc_b32:$src0, VCSrc_b32:$src1), -10>,
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Requires<[HasAddNoCarryInsts]>;
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def : InstAlias<Inst#" $vdst, vcc, $src0, $src1",
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(Inst32CO VGPR_32:$vdst, VSrc_b32:$src0, VGPR_32:$src1), 1000>,
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Requires<[HasAddNoCarryInsts]>;
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def : InstAlias<Inst#" $vdst, $sdst, $src0, $src1",
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(Inst64CO VGPR_32:$vdst, SReg_64:$sdst, VSrc_b32:$src0, VGPR_32:$src1), -10>,
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Requires<[HasAddNoCarryInsts]>;
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}
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// gfx9 made a mess of add instruction names. The existing add
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// instructions add _co added to the names, and their old names were
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// repurposed to a version without carry out.
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let Predicates = [HasAddNoCarryInsts] in {
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defm : NoCarryAlias<"v_add_u32", V_ADD_U32_e32_vi, V_ADD_U32_e64_vi,
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V_ADD_I32_e32_vi, V_ADD_I32_e64_vi>;
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defm : NoCarryAlias<"v_sub_u32", V_SUB_U32_e32_vi, V_SUB_U32_e64_vi,
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V_SUB_I32_e32_vi, V_SUB_I32_e64_vi>;
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defm : NoCarryAlias<"v_subrev_u32",
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V_SUBREV_U32_e32_vi, V_SUBREV_U32_e64_vi,
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V_SUBREV_I32_e32_vi, V_SUBREV_I32_e64_vi>;
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}
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let Predicates = [NotHasAddNoCarryInsts] in {
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def : MnemonicAlias<"v_add_u32", "v_add_i32">;
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def : MnemonicAlias<"v_sub_u32", "v_sub_i32">;
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def : MnemonicAlias<"v_subrev_u32", "v_subrev_i32">;
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}
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} // End isGCN predicate
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@ -375,6 +375,14 @@ defm V_SUBREV_I32 : VOP2bInst <"v_subrev_i32", VOP2b_I32_I1_I32_I32, null_frag,
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defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1>;
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defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1>;
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defm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32">;
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let SubtargetPredicate = HasAddNoCarryInsts in {
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defm V_ADD_U32 : VOP2Inst <"v_add_u32", VOP_I32_I32_I32>;
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defm V_SUB_U32 : VOP2Inst <"v_sub_u32", VOP_I32_I32_I32>;
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defm V_SUBREV_U32 : VOP2Inst <"v_subrev_u32", VOP_I32_I32_I32, null_frag, "v_sub_u32">;
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}
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} // End isCommutable = 1
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// These are special and do not read the exec mask.
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@ -833,3 +841,9 @@ def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>;
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def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>;
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} // End SubtargetPredicate = isVI
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let SubtargetPredicate = HasAddNoCarryInsts in {
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defm V_ADD_U32 : VOP2_Real_e32e64_vi <0x34>;
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defm V_SUB_U32 : VOP2_Real_e32e64_vi <0x35>;
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defm V_SUBREV_U32 : VOP2_Real_e32e64_vi <0x36>;
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}
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@ -0,0 +1,104 @@
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// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefixes=GCN,GFX9 %s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck -check-prefixes=GCN,VI %s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck -check-prefixes=ERR-SICIVI %s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck -check-prefixes=ERR-SICIVI %s
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// FIXME: pre-gfx9 errors should be more useful
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// FIXME: These should parse to VOP2 encoding
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v_add_u32 v1, v2, v3
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// GFX9: v_add_u32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x34,0xd1,0x02,0x07,0x02,0x00]
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// ERR-SICIVI: :15: error: invalid operand for instruction
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v_add_u32 v1, v2, s1
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// GFX9: v_add_u32_e64 v1, v2, s1 ; encoding: [0x01,0x00,0x34,0xd1,0x02,0x03,0x00,0x00]
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// ERR-SICIVI: :15: error: invalid operand for instruction
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v_add_u32 v1, s1, v2
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// GFX9: v_add_u32_e64 v1, s1, v2 ; encoding: [0x01,0x00,0x34,0xd1,0x01,0x04,0x02,0x00]
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// ERR-SICIVI: :15: error: invalid operand for instruction
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v_add_u32 v1, 4.0, v2
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// GFX9: v_add_u32_e64 v1, 4.0, v2 ; encoding: [0x01,0x00,0x34,0xd1,0xf6,0x04,0x02,0x00]
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// ERR-SICIVI: :15: error: invalid operand for instruction
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v_add_u32 v1, v2, 4.0
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// GFX9: v_add_u32_e64 v1, v2, 4.0 ; encoding: [0x01,0x00,0x34,0xd1,0x02,0xed,0x01,0x00]
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// ERR-SICIVI: :15: error: invalid operand for instruction
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v_add_u32_e32 v1, v2, v3
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// GFX9: v_add_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x68]
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// ERR-SICIVI: :19: error: invalid operand for instruction
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v_add_u32_e32 v1, s1, v3
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// GFX9: v_add_u32_e32 v1, s1, v3 ; encoding: [0x01,0x06,0x02,0x68]
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// ERR-SICIVI: :19: error: invalid operand for instruction
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v_sub_u32 v1, v2, v3
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// GFX9: v_sub_u32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x35,0xd1,0x02,0x07,0x02,0x00]
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// ERR-SICIVI: :15: error: invalid operand for instruction
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v_sub_u32 v1, v2, s1
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// GFX9: v_sub_u32_e64 v1, v2, s1 ; encoding: [0x01,0x00,0x35,0xd1,0x02,0x03,0x00,0x00]
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// ERR-SICIVI: :15: error: invalid operand for instruction
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v_sub_u32 v1, s1, v2
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// GFX9: v_sub_u32_e64 v1, s1, v2 ; encoding: [0x01,0x00,0x35,0xd1,0x01,0x04,0x02,0x00]
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// ERR-SICIVI: :15: error: invalid operand for instruction
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v_sub_u32 v1, 4.0, v2
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// GFX9: v_sub_u32_e64 v1, 4.0, v2 ; encoding: [0x01,0x00,0x35,0xd1,0xf6,0x04,0x02,0x00]
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// ERR-SICIVI: :15: error: invalid operand for instruction
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v_sub_u32 v1, v2, 4.0
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// GFX9: v_sub_u32_e64 v1, v2, 4.0 ; encoding: [0x01,0x00,0x35,0xd1,0x02,0xed,0x01,0x00]
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// ERR-SICIVI: :15: error: invalid operand for instruction
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v_sub_u32_e32 v1, v2, v3
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// GFX9: v_sub_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x6a]
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// ERR-SICIVI: :19: error: invalid operand for instruction
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v_sub_u32_e32 v1, s1, v3
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// GFX9: v_sub_u32_e32 v1, s1, v3 ; encoding: [0x01,0x06,0x02,0x6a]
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// ERR-SICIVI: :19: error: invalid operand for instruction
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v_subrev_u32 v1, v2, v3
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// GFX9: v_subrev_u32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x36,0xd1,0x02,0x07,0x02,0x00]
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// ERR-SICIVI: :18: error: invalid operand for instruction
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v_subrev_u32 v1, v2, s1
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// GFX9: v_subrev_u32_e64 v1, v2, s1 ; encoding: [0x01,0x00,0x36,0xd1,0x02,0x03,0x00,0x00]
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// ERR-SICIVI: :18: error: invalid operand for instruction
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v_subrev_u32 v1, s1, v2
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// GFX9: v_subrev_u32_e64 v1, s1, v2 ; encoding: [0x01,0x00,0x36,0xd1,0x01,0x04,0x02,0x00]
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// ERR-SICIVI: :18: error: invalid operand for instruction
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v_subrev_u32 v1, 4.0, v2
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// GFX9: v_subrev_u32_e64 v1, 4.0, v2 ; encoding: [0x01,0x00,0x36,0xd1,0xf6,0x04,0x02,0x00]
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// ERR-SICIVI: :18: error: invalid operand for instruction
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v_subrev_u32 v1, v2, 4.0
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// GFX9: v_subrev_u32_e64 v1, v2, 4.0 ; encoding: [0x01,0x00,0x36,0xd1,0x02,0xed,0x01,0x00]
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// ERR-SICIVI: :18: error: invalid operand for instruction
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v_subrev_u32_e32 v1, v2, v3
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// GFX9: v_subrev_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x6c]
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// ERR-SICIVI: :22: error: invalid operand for instruction
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v_subrev_u32_e32 v1, s1, v3
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// GFX9: v_subrev_u32_e32 v1, s1, v3 ; encoding: [0x01,0x06,0x02,0x6c]
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// ERR-SICIVI: :22: error: invalid operand for instruction
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v_add_u32 v1, vcc, v2, v3
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// GCN: v_add_i32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x32]
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v_add_u32 v1, s[0:1], v2, v3
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// GCN: v_add_i32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x19,0xd1,0x02,0x07,0x02,0x00]
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