replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Simplify iterator usage now that we have next(). Also don't pass iterators by reference now that MachineInstr* are in an ilist 

llvm-svn: 11732
This commit is contained in:
Alkis Evlogimenos 2004-02-23 04:12:30 +00:00
parent e0f79a6a55
commit c31ff795d5
1 changed files with 7 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
llvm/lib/CodeGen/RegAllocSimple.cpp
View File

@ -24,6 +24,7 @@
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "Support/Debug.h" #include "Support/Debug.h"
#include "Support/Statistic.h" #include "Support/Statistic.h"
#include "Support/STLExtras.h"
#include <iostream> #include <iostream>
using namespace llvm; using namespace llvm;
@ -78,10 +79,10 @@ namespace {
/// Moves value from memory into that register /// Moves value from memory into that register
unsigned reloadVirtReg(MachineBasicBlock &MBB, unsigned reloadVirtReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &I, unsigned VirtReg); MachineBasicBlock::iterator I, unsigned VirtReg);
/// Saves reg value on the stack (maps virtual register to stack value) /// Saves reg value on the stack (maps virtual register to stack value)
void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg); unsigned VirtReg, unsigned PhysReg);
}; };
@ -123,7 +124,7 @@ unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
} }
unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB, unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &I, MachineBasicBlock::iterator I,
unsigned VirtReg) { unsigned VirtReg) {
const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg); const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg);
int FrameIdx = getStackSpaceFor(VirtReg, RC); int FrameIdx = getStackSpaceFor(VirtReg, RC);
@ -136,7 +137,7 @@ unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
} }
void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB, void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &I, MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg) { unsigned VirtReg, unsigned PhysReg) {
const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg); const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg);
int FrameIdx = getStackSpaceFor(VirtReg, RC); int FrameIdx = getStackSpaceFor(VirtReg, RC);
@ -193,17 +194,12 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
"Two address instruction invalid!"); "Two address instruction invalid!");
physReg = MI->getOperand(1).getReg(); physReg = MI->getOperand(1).getReg();
spillVirtReg(MBB, next(MI), virtualReg, physReg);
++MI;
spillVirtReg(MBB, MI, virtualReg, physReg);
--MI;
MI->getOperand(1).setDef(); MI->getOperand(1).setDef();
MI->RemoveOperand(0); MI->RemoveOperand(0);
break; // This is the last operand to process break; // This is the last operand to process
} }
++MI; spillVirtReg(MBB, next(MI), virtualReg, physReg);
spillVirtReg(MBB, MI, virtualReg, physReg);
--MI;
} else { } else {
physReg = reloadVirtReg(MBB, MI, virtualReg); physReg = reloadVirtReg(MBB, MI, virtualReg);
Virt2PhysRegMap[virtualReg] = physReg; Virt2PhysRegMap[virtualReg] = physReg;