[PowerPC] Add Itineraries of IIC_IntRotateDI for P7/P8
When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. Patch by jsji (Jinsong Ji) Differential Revision: https://reviews.llvm.org/D51506 llvm-svn: 341293
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@ -126,6 +126,10 @@ def P7Itineraries : ProcessorItineraries<
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_IntRotateDI , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_IntShift , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_FX1, P7_FX2]>],
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@ -102,6 +102,10 @@ def P8Itineraries : ProcessorItineraries<
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_IntRotateDI , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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[1, 1, 1]>,
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InstrItinData<IIC_IntShift , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
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P8_DU4, P8_DU5, P8_DU6], 0>,
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InstrStage<1, [P8_FXU1, P8_FXU2]>],
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@ -33,20 +33,20 @@ define signext i32 @main() {
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;
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; CHECK-P7-LABEL: main:
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; CHECK-P7: li 3, -32477
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; CHECK-P7: lis 4, 0
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; CHECK-P7: lis 5, 0
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; CHECK-P7: li 7, 0
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; CHECK-P7: li 5, 234
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; CHECK-P7: sth 3, 46(1)
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; CHECK-P7: ori 4, 4, 33059
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; CHECK-P7: rlwinm 3, 6, 3, 27, 27
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; CHECK-P7: li 6, 234
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; CHECK-P7: ori 5, 5, 33059
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; CHECK-P7: rlwinm 3, 4, 3, 27, 27
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; CHECK-P7: ori 7, 7, 65535
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; CHECK-P7: sync
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; CHECK-P7: slw 6, 6, 3
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; CHECK-P7: slw 8, 5, 3
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; CHECK-P7: slw 9, 4, 3
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; CHECK-P7: rldicr 4, 6, 0, 61
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; CHECK-P7: slw 5, 7, 3
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; CHECK-P7: and 7, 8, 5
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; CHECK-P7: and 8, 9, 5
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; CHECK-P7: rldicr 4, 4, 0, 61
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; CHECK-P7: and 7, 6, 5
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; CHECK-P7: and 8, 8, 5
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; CHECK-P7: .LBB0_1: # %L.entry
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; CHECK-P7: lwarx 9, 0, 4
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; CHECK-P7: and 6, 9, 5
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@ -36,8 +36,8 @@ define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) {
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; CHECK: # %bb.0:
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; CHECK-NEXT: lis 6, -8857
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; CHECK-NEXT: clrldi 5, 5, 27
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; CHECK-NEXT: clrldi 4, 4, 27
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; CHECK-NEXT: ori 6, 6, 51366
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; CHECK-NEXT: clrldi 4, 4, 27
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; CHECK-NEXT: sldi 6, 6, 32
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; CHECK-NEXT: oris 6, 6, 3542
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; CHECK-NEXT: ori 6, 6, 31883
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@ -71,49 +71,49 @@ define i64 @ReverseBits64(i64 %n) {
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lis 4, -21846
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; CHECK-NEXT: lis 5, 21845
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; CHECK-NEXT: lis 6, -13108
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; CHECK-NEXT: lis 7, 13107
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; CHECK-NEXT: sldi 8, 3, 1
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; CHECK-NEXT: rldicl 3, 3, 63, 1
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; CHECK-NEXT: lis 7, -13108
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; CHECK-NEXT: lis 8, 13107
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; CHECK-NEXT: ori 4, 4, 43690
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; CHECK-NEXT: ori 5, 5, 21845
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; CHECK-NEXT: ori 6, 6, 52428
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; CHECK-NEXT: ori 7, 7, 13107
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; CHECK-NEXT: ori 7, 7, 52428
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; CHECK-NEXT: ori 8, 8, 13107
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; CHECK-NEXT: sldi 4, 4, 32
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; CHECK-NEXT: sldi 5, 5, 32
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; CHECK-NEXT: oris 4, 4, 43690
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; CHECK-NEXT: oris 5, 5, 21845
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; CHECK-NEXT: sldi 6, 3, 1
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; CHECK-NEXT: rldicl 3, 3, 63, 1
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; CHECK-NEXT: ori 4, 4, 43690
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; CHECK-NEXT: ori 5, 5, 21845
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; CHECK-NEXT: and 4, 8, 4
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; CHECK-NEXT: and 3, 3, 5
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; CHECK-NEXT: sldi 5, 6, 32
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; CHECK-NEXT: sldi 6, 7, 32
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; CHECK-NEXT: lis 7, 3855
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: oris 4, 5, 52428
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; CHECK-NEXT: oris 5, 6, 13107
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; CHECK-NEXT: lis 6, -3856
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; CHECK-NEXT: ori 7, 7, 3855
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; CHECK-NEXT: sldi 8, 3, 2
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; CHECK-NEXT: ori 4, 4, 52428
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; CHECK-NEXT: rldicl 3, 3, 62, 2
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; CHECK-NEXT: ori 5, 5, 13107
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; CHECK-NEXT: ori 6, 6, 61680
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; CHECK-NEXT: and 4, 8, 4
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; CHECK-NEXT: and 3, 3, 5
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; CHECK-NEXT: sldi 5, 6, 32
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; CHECK-NEXT: sldi 6, 7, 32
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: oris 4, 5, 61680
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; CHECK-NEXT: oris 5, 6, 3855
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; CHECK-NEXT: sldi 6, 3, 4
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; CHECK-NEXT: ori 4, 4, 61680
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; CHECK-NEXT: rldicl 3, 3, 60, 4
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; CHECK-NEXT: ori 5, 5, 3855
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; CHECK-NEXT: sldi 7, 7, 32
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; CHECK-NEXT: sldi 8, 8, 32
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; CHECK-NEXT: and 4, 6, 4
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; CHECK-NEXT: and 3, 3, 5
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; CHECK-NEXT: lis 5, -3856
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; CHECK-NEXT: oris 6, 7, 52428
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; CHECK-NEXT: oris 7, 8, 13107
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: lis 4, 3855
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; CHECK-NEXT: ori 5, 5, 61680
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; CHECK-NEXT: ori 6, 6, 52428
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; CHECK-NEXT: ori 7, 7, 13107
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; CHECK-NEXT: ori 4, 4, 3855
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; CHECK-NEXT: sldi 8, 3, 2
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; CHECK-NEXT: rldicl 3, 3, 62, 2
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; CHECK-NEXT: and 6, 8, 6
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; CHECK-NEXT: and 3, 3, 7
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; CHECK-NEXT: sldi 5, 5, 32
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; CHECK-NEXT: sldi 4, 4, 32
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; CHECK-NEXT: or 3, 3, 6
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; CHECK-NEXT: oris 5, 5, 61680
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; CHECK-NEXT: oris 4, 4, 3855
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; CHECK-NEXT: sldi 6, 3, 4
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; CHECK-NEXT: ori 5, 5, 61680
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; CHECK-NEXT: ori 4, 4, 3855
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; CHECK-NEXT: rldicl 3, 3, 60, 4
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; CHECK-NEXT: and 5, 6, 5
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; CHECK-NEXT: and 3, 3, 4
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; CHECK-NEXT: or 3, 3, 5
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; CHECK-NEXT: rldicl 4, 3, 32, 32
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; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31
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; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31
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@ -47,49 +47,49 @@ define i64 @testBitReverseIntrinsicI64(i64 %arg) {
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; CHECK: # %bb.0:
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; CHECK-NEXT: lis 4, -21846
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; CHECK-NEXT: lis 5, 21845
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; CHECK-NEXT: lis 6, -13108
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; CHECK-NEXT: lis 7, 13107
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; CHECK-NEXT: sldi 8, 3, 1
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; CHECK-NEXT: rldicl 3, 3, 63, 1
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; CHECK-NEXT: lis 7, -13108
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; CHECK-NEXT: lis 8, 13107
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; CHECK-NEXT: ori 4, 4, 43690
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; CHECK-NEXT: ori 5, 5, 21845
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; CHECK-NEXT: ori 6, 6, 52428
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; CHECK-NEXT: ori 7, 7, 13107
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; CHECK-NEXT: ori 7, 7, 52428
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; CHECK-NEXT: ori 8, 8, 13107
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; CHECK-NEXT: sldi 4, 4, 32
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; CHECK-NEXT: sldi 5, 5, 32
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; CHECK-NEXT: oris 4, 4, 43690
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; CHECK-NEXT: oris 5, 5, 21845
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; CHECK-NEXT: sldi 6, 3, 1
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; CHECK-NEXT: rldicl 3, 3, 63, 1
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; CHECK-NEXT: ori 4, 4, 43690
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; CHECK-NEXT: ori 5, 5, 21845
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; CHECK-NEXT: and 4, 8, 4
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; CHECK-NEXT: and 3, 3, 5
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; CHECK-NEXT: sldi 5, 6, 32
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; CHECK-NEXT: sldi 6, 7, 32
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; CHECK-NEXT: lis 7, 3855
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: oris 4, 5, 52428
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; CHECK-NEXT: oris 5, 6, 13107
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; CHECK-NEXT: lis 6, -3856
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; CHECK-NEXT: ori 7, 7, 3855
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; CHECK-NEXT: sldi 8, 3, 2
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; CHECK-NEXT: ori 4, 4, 52428
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; CHECK-NEXT: rldicl 3, 3, 62, 2
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; CHECK-NEXT: ori 5, 5, 13107
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; CHECK-NEXT: ori 6, 6, 61680
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; CHECK-NEXT: and 4, 8, 4
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; CHECK-NEXT: and 3, 3, 5
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; CHECK-NEXT: sldi 5, 6, 32
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; CHECK-NEXT: sldi 6, 7, 32
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: oris 4, 5, 61680
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; CHECK-NEXT: oris 5, 6, 3855
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; CHECK-NEXT: sldi 6, 3, 4
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; CHECK-NEXT: ori 4, 4, 61680
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; CHECK-NEXT: rldicl 3, 3, 60, 4
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; CHECK-NEXT: ori 5, 5, 3855
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; CHECK-NEXT: sldi 7, 7, 32
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; CHECK-NEXT: sldi 8, 8, 32
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; CHECK-NEXT: and 4, 6, 4
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; CHECK-NEXT: and 3, 3, 5
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; CHECK-NEXT: lis 5, -3856
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; CHECK-NEXT: oris 6, 7, 52428
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; CHECK-NEXT: oris 7, 8, 13107
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: lis 4, 3855
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; CHECK-NEXT: ori 5, 5, 61680
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; CHECK-NEXT: ori 6, 6, 52428
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; CHECK-NEXT: ori 7, 7, 13107
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; CHECK-NEXT: ori 4, 4, 3855
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; CHECK-NEXT: sldi 8, 3, 2
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; CHECK-NEXT: rldicl 3, 3, 62, 2
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; CHECK-NEXT: and 6, 8, 6
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; CHECK-NEXT: and 3, 3, 7
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; CHECK-NEXT: sldi 5, 5, 32
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; CHECK-NEXT: sldi 4, 4, 32
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; CHECK-NEXT: or 3, 3, 6
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; CHECK-NEXT: oris 5, 5, 61680
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; CHECK-NEXT: oris 4, 4, 3855
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; CHECK-NEXT: sldi 6, 3, 4
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; CHECK-NEXT: ori 5, 5, 61680
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; CHECK-NEXT: ori 4, 4, 3855
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; CHECK-NEXT: rldicl 3, 3, 60, 4
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; CHECK-NEXT: and 5, 6, 5
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; CHECK-NEXT: and 3, 3, 4
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; CHECK-NEXT: or 3, 3, 5
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; CHECK-NEXT: rldicl 4, 3, 32, 32
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; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31
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; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31
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