Add ARMTargetCodeGenInfo::initDwarfEHRegSizeTable() defining 16 32bit regs.
llvm-svn: 131558
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@ -2279,6 +2279,22 @@ public:
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int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const {
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int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const {
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return 13;
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return 13;
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}
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}
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bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
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llvm::Value *Address) const {
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CodeGen::CGBuilderTy &Builder = CGF.Builder;
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llvm::LLVMContext &Context = CGF.getLLVMContext();
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const llvm::IntegerType *i8 = llvm::Type::getInt8Ty(Context);
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llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
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// 0-15 are the 16 integer registers.
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AssignToArrayRange(Builder, Address, Four8, 0, 15);
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return false;
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}
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};
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};
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}
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}
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