Implement branch analysis/xform hooks required by the branch folding pass.
llvm-svn: 31065
This commit is contained in:
Chris Lattner
parent
a91e4be84f
commit
c0fb567e23
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@ -2317,30 +2317,6 @@ LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
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return std::make_pair(Result, Chain);
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}
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/// getCondBrOpcodeForX86CC - Returns the X86 conditional branch opcode
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/// which corresponds to the condition code.
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static unsigned getCondBrOpcodeForX86CC(unsigned X86CC) {
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switch (X86CC) {
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default: assert(0 && "Unknown X86 conditional code!");
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case X86ISD::COND_A: return X86::JA;
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case X86ISD::COND_AE: return X86::JAE;
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case X86ISD::COND_B: return X86::JB;
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case X86ISD::COND_BE: return X86::JBE;
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case X86ISD::COND_E: return X86::JE;
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case X86ISD::COND_G: return X86::JG;
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case X86ISD::COND_GE: return X86::JGE;
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case X86ISD::COND_L: return X86::JL;
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case X86ISD::COND_LE: return X86::JLE;
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case X86ISD::COND_NE: return X86::JNE;
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case X86ISD::COND_NO: return X86::JNO;
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case X86ISD::COND_NP: return X86::JNP;
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case X86ISD::COND_NS: return X86::JNS;
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case X86ISD::COND_O: return X86::JO;
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case X86ISD::COND_P: return X86::JP;
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case X86ISD::COND_S: return X86::JS;
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}
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}
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/// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
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/// specific condition code. It returns a false if it cannot do a direct
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/// translation. X86CC is the translated CondCode. LHS/RHS are modified as
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@ -2348,33 +2324,33 @@ static unsigned getCondBrOpcodeForX86CC(unsigned X86CC) {
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static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
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unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
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SelectionDAG &DAG) {
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X86CC = X86ISD::COND_INVALID;
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X86CC = X86::COND_INVALID;
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if (!isFP) {
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if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
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if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
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// X > -1 -> X == 0, jump !sign.
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RHS = DAG.getConstant(0, RHS.getValueType());
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X86CC = X86ISD::COND_NS;
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X86CC = X86::COND_NS;
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return true;
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} else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
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// X < 0 -> X == 0, jump on sign.
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X86CC = X86ISD::COND_S;
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X86CC = X86::COND_S;
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return true;
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}
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}
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switch (SetCCOpcode) {
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default: break;
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case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
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case ISD::SETGT: X86CC = X86ISD::COND_G; break;
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case ISD::SETGE: X86CC = X86ISD::COND_GE; break;
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case ISD::SETLT: X86CC = X86ISD::COND_L; break;
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case ISD::SETLE: X86CC = X86ISD::COND_LE; break;
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case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
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case ISD::SETULT: X86CC = X86ISD::COND_B; break;
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case ISD::SETUGT: X86CC = X86ISD::COND_A; break;
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case ISD::SETULE: X86CC = X86ISD::COND_BE; break;
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case ISD::SETUGE: X86CC = X86ISD::COND_AE; break;
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case ISD::SETEQ: X86CC = X86::COND_E; break;
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case ISD::SETGT: X86CC = X86::COND_G; break;
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case ISD::SETGE: X86CC = X86::COND_GE; break;
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case ISD::SETLT: X86CC = X86::COND_L; break;
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case ISD::SETLE: X86CC = X86::COND_LE; break;
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case ISD::SETNE: X86CC = X86::COND_NE; break;
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case ISD::SETULT: X86CC = X86::COND_B; break;
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case ISD::SETUGT: X86CC = X86::COND_A; break;
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case ISD::SETULE: X86CC = X86::COND_BE; break;
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case ISD::SETUGE: X86CC = X86::COND_AE; break;
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}
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} else {
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// On a floating point condition, the flags are set as follows:
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@ -2387,29 +2363,29 @@ static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
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switch (SetCCOpcode) {
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default: break;
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case ISD::SETUEQ:
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case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
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case ISD::SETEQ: X86CC = X86::COND_E; break;
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case ISD::SETOLT: Flip = true; // Fallthrough
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case ISD::SETOGT:
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case ISD::SETGT: X86CC = X86ISD::COND_A; break;
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case ISD::SETGT: X86CC = X86::COND_A; break;
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case ISD::SETOLE: Flip = true; // Fallthrough
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case ISD::SETOGE:
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case ISD::SETGE: X86CC = X86ISD::COND_AE; break;
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case ISD::SETGE: X86CC = X86::COND_AE; break;
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case ISD::SETUGT: Flip = true; // Fallthrough
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case ISD::SETULT:
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case ISD::SETLT: X86CC = X86ISD::COND_B; break;
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case ISD::SETLT: X86CC = X86::COND_B; break;
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case ISD::SETUGE: Flip = true; // Fallthrough
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case ISD::SETULE:
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case ISD::SETLE: X86CC = X86ISD::COND_BE; break;
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case ISD::SETLE: X86CC = X86::COND_BE; break;
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case ISD::SETONE:
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case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
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case ISD::SETUO: X86CC = X86ISD::COND_P; break;
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case ISD::SETO: X86CC = X86ISD::COND_NP; break;
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case ISD::SETNE: X86CC = X86::COND_NE; break;
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case ISD::SETUO: X86CC = X86::COND_P; break;
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case ISD::SETO: X86CC = X86::COND_NP; break;
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}
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if (Flip)
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std::swap(LHS, RHS);
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}
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return X86CC != X86ISD::COND_INVALID;
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return X86CC != X86::COND_INVALID;
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}
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/// hasFPCMov - is there a floating point cmov for the specific X86 condition
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@ -2419,14 +2395,14 @@ static bool hasFPCMov(unsigned X86CC) {
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switch (X86CC) {
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default:
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return false;
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case X86ISD::COND_B:
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case X86ISD::COND_BE:
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case X86ISD::COND_E:
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case X86ISD::COND_P:
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case X86ISD::COND_A:
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case X86ISD::COND_AE:
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case X86ISD::COND_NE:
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case X86ISD::COND_NP:
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case X86::COND_B:
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case X86::COND_BE:
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case X86::COND_E:
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case X86::COND_P:
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case X86::COND_A:
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case X86::COND_AE:
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case X86::COND_NE:
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case X86::COND_NP:
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return true;
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}
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}
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@ -3928,7 +3904,7 @@ SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
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SDOperand InFlag = DAG.getNode(X86ISD::CMP, VTs, 2, COps, 3).getValue(1);
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SDOperand Hi, Lo;
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SDOperand CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
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SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
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VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
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SmallVector<SDOperand, 4> Ops;
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@ -4148,17 +4124,17 @@ SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG,
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switch (SetCCOpcode) {
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default: assert(false && "Illegal floating point SetCC!");
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case ISD::SETOEQ: { // !PF & ZF
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SDOperand Ops1[] = { DAG.getConstant(X86ISD::COND_NP, MVT::i8), Cond };
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SDOperand Ops1[] = { DAG.getConstant(X86::COND_NP, MVT::i8), Cond };
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SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
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SDOperand Ops2[] = { DAG.getConstant(X86ISD::COND_E, MVT::i8),
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SDOperand Ops2[] = { DAG.getConstant(X86::COND_E, MVT::i8),
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Tmp1.getValue(1) };
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SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
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return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
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}
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case ISD::SETUNE: { // PF | !ZF
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SDOperand Ops1[] = { DAG.getConstant(X86ISD::COND_P, MVT::i8), Cond };
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SDOperand Ops1[] = { DAG.getConstant(X86::COND_P, MVT::i8), Cond };
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SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
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SDOperand Ops2[] = { DAG.getConstant(X86ISD::COND_NE, MVT::i8),
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SDOperand Ops2[] = { DAG.getConstant(X86::COND_NE, MVT::i8),
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Tmp1.getValue(1) };
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SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
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return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
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@ -4199,7 +4175,7 @@ SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
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}
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if (addTest) {
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CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
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CC = DAG.getConstant(X86::COND_NE, MVT::i8);
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SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
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Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
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}
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@ -4245,7 +4221,7 @@ SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
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}
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if (addTest) {
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CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
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CC = DAG.getConstant(X86::COND_NE, MVT::i8);
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SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
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Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
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}
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@ -5069,7 +5045,8 @@ X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *thisMBB = BB;
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MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
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unsigned Opc = getCondBrOpcodeForX86CC(MI->getOperand(3).getImmedValue());
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unsigned Opc =
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X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
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BuildMI(BB, Opc, 1).addMBB(sinkMBB);
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MachineFunction *F = BB->getParent();
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F->getBasicBlockList().insert(It, copy0MBB);
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@ -5149,15 +5126,15 @@ X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
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}
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Op = MI->getOperand(1);
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if (Op.isImmediate())
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AM.Scale = Op.getImmedValue();
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AM.Scale = Op.getImm();
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Op = MI->getOperand(2);
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if (Op.isImmediate())
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AM.IndexReg = Op.getImmedValue();
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AM.IndexReg = Op.getImm();
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Op = MI->getOperand(3);
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if (Op.isGlobalAddress()) {
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AM.GV = Op.getGlobal();
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} else {
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AM.Disp = Op.getImmedValue();
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AM.Disp = Op.getImm();
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}
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addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(MI->getOperand(4).getReg());
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@ -162,28 +162,6 @@ namespace llvm {
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/// corresponds to X86::PINSRW.
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PINSRW
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};
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// X86 specific condition code. These correspond to X86_*_COND in
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// X86InstrInfo.td. They must be kept in synch.
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enum CondCode {
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COND_A = 0,
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COND_AE = 1,
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COND_B = 2,
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COND_BE = 3,
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COND_E = 4,
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COND_G = 5,
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COND_GE = 6,
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COND_L = 7,
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COND_LE = 8,
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COND_NE = 9,
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COND_NO = 10,
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COND_NP = 11,
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COND_NS = 12,
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COND_O = 13,
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COND_P = 14,
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COND_S = 15,
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COND_INVALID
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};
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}
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/// Define some predicates that are used for node matching.
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@ -246,6 +246,157 @@ MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
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}
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}
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static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
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switch (BrOpc) {
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default: return X86::COND_INVALID;
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case X86::JE: return X86::COND_E;
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case X86::JNE: return X86::COND_NE;
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case X86::JL: return X86::COND_L;
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case X86::JLE: return X86::COND_LE;
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case X86::JG: return X86::COND_G;
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case X86::JGE: return X86::COND_GE;
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case X86::JB: return X86::COND_B;
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case X86::JBE: return X86::COND_BE;
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case X86::JA: return X86::COND_A;
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case X86::JAE: return X86::COND_AE;
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case X86::JS: return X86::COND_S;
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case X86::JNS: return X86::COND_NS;
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case X86::JP: return X86::COND_P;
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case X86::JNP: return X86::COND_NP;
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case X86::JO: return X86::COND_O;
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case X86::JNO: return X86::COND_NO;
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}
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}
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unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
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switch (CC) {
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default: assert(0 && "Illegal condition code!");
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case X86::COND_E: return X86::JE;
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case X86::COND_NE: return X86::JNE;
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case X86::COND_L: return X86::JL;
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case X86::COND_LE: return X86::JLE;
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case X86::COND_G: return X86::JG;
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case X86::COND_GE: return X86::JGE;
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case X86::COND_B: return X86::JB;
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case X86::COND_BE: return X86::JBE;
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case X86::COND_A: return X86::JA;
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case X86::COND_AE: return X86::JAE;
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case X86::COND_S: return X86::JS;
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case X86::COND_NS: return X86::JNS;
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case X86::COND_P: return X86::JP;
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case X86::COND_NP: return X86::JNP;
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case X86::COND_O: return X86::JO;
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case X86::COND_NO: return X86::JNO;
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}
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}
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bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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std::vector<MachineOperand> &Cond) const {
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// TODO: If FP_REG_KILL is around, ignore it.
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode()))
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return false;
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// Get the last instruction in the block.
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MachineInstr *LastInst = I;
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// If there is only one terminator instruction, process it.
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if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) {
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if (!isBranch(LastInst->getOpcode()))
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return true;
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// If the block ends with a branch there are 3 possibilities:
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// it's an unconditional, conditional, or indirect branch.
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if (LastInst->getOpcode() == X86::JMP) {
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TBB = LastInst->getOperand(0).getMachineBasicBlock();
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return false;
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}
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X86::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
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if (BranchCode == X86::COND_INVALID)
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return true; // Can't handle indirect branch.
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// Otherwise, block ends with fall-through condbranch.
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TBB = LastInst->getOperand(0).getMachineBasicBlock();
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Cond.push_back(MachineOperand::CreateImm(BranchCode));
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return false;
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}
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// Get the instruction before it if it's a terminator.
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MachineInstr *SecondLastInst = I;
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// If there are three terminators, we don't know what sort of block this is.
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if (SecondLastInst && I != MBB.begin() &&
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isTerminatorInstr((--I)->getOpcode()))
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return true;
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// If the block ends with X86::JMP and a COND_BRANCH, handle it.
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X86::CondCode BranchCode = GetCondFromBranchOpc(SecondLastInst->getOpcode());
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if (BranchCode != X86::COND_INVALID && LastInst->getOpcode() == X86::JMP) {
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TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
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Cond.push_back(MachineOperand::CreateImm(BranchCode));
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FBB = LastInst->getOperand(0).getMachineBasicBlock();
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return false;
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}
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// Otherwise, can't handle this.
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return true;
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}
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void X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin()) return;
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--I;
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if (I->getOpcode() != X86::JMP &&
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GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
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return;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.end();
|
||||
|
||||
if (I == MBB.begin()) return;
|
||||
--I;
|
||||
if (GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
|
||||
return;
|
||||
|
||||
// Remove the branch.
|
||||
I->eraseFromParent();
|
||||
}
|
||||
|
||||
void X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const std::vector<MachineOperand> &Cond) const {
|
||||
// Shouldn't be a fall through.
|
||||
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
||||
|
||||
// Unconditional branch?
|
||||
if (FBB == 0) {
|
||||
BuildMI(&MBB, X86::JMP, 1).addMBB(TBB);
|
||||
return;
|
||||
}
|
||||
|
||||
assert(Cond.size() == 2 && "PPC branch conditions have two components!");
|
||||
|
||||
// Conditional branch.
|
||||
unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
|
||||
BuildMI(&MBB, Opc, 1).addMBB(TBB);
|
||||
|
||||
if (FBB) // Two-way branch.
|
||||
BuildMI(&MBB, X86::JMP, 1).addMBB(FBB);
|
||||
}
|
||||
|
||||
bool X86InstrInfo::
|
||||
ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
|
||||
// TODO: IMPLEMENT.
|
||||
return true;
|
||||
}
|
||||
|
||||
const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
|
||||
const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
|
||||
if (Subtarget->is64Bit())
|
||||
|
|
|
|||
|
|
@ -21,6 +21,33 @@ namespace llvm {
|
|||
class X86RegisterInfo;
|
||||
class X86TargetMachine;
|
||||
|
||||
namespace X86 {
|
||||
// X86 specific condition code. These correspond to X86_*_COND in
|
||||
// X86InstrInfo.td. They must be kept in synch.
|
||||
enum CondCode {
|
||||
COND_A = 0,
|
||||
COND_AE = 1,
|
||||
COND_B = 2,
|
||||
COND_BE = 3,
|
||||
COND_E = 4,
|
||||
COND_G = 5,
|
||||
COND_GE = 6,
|
||||
COND_L = 7,
|
||||
COND_LE = 8,
|
||||
COND_NE = 9,
|
||||
COND_NO = 10,
|
||||
COND_NP = 11,
|
||||
COND_NS = 12,
|
||||
COND_O = 13,
|
||||
COND_P = 14,
|
||||
COND_S = 15,
|
||||
COND_INVALID
|
||||
};
|
||||
|
||||
// Turn condition code into conditional branch opcode.
|
||||
unsigned GetCondBranchFromCond(CondCode CC);
|
||||
}
|
||||
|
||||
/// X86II - This namespace holds all of the target specific flags that
|
||||
/// instruction info tracks.
|
||||
///
|
||||
|
|
@ -227,6 +254,15 @@ public:
|
|||
///
|
||||
virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
|
||||
|
||||
// Branch analysis.
|
||||
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
|
||||
MachineBasicBlock *&FBB,
|
||||
std::vector<MachineOperand> &Cond) const;
|
||||
virtual void RemoveBranch(MachineBasicBlock &MBB) const;
|
||||
virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const std::vector<MachineOperand> &Cond) const;
|
||||
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
|
||||
|
||||
const TargetRegisterClass *getPointerRegClass() const;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue