AMDGPU: Factor out EOP query.
v2: Fix brace placement and capitalization (Matt). Patch by: Zoltan Gilian llvm-svn: 249041
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@ -190,6 +190,10 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM,
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setSchedulingPreference(Sched::Source);
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}
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static inline bool isEOP(MachineBasicBlock::iterator I) {
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return std::next(I)->getOpcode() == AMDGPU::RETURN;
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}
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MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
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MachineInstr * MI, MachineBasicBlock * BB) const {
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MachineFunction * MF = BB->getParent();
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@ -276,12 +280,10 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
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case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
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case AMDGPU::RAT_WRITE_CACHELESS_64_eg:
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case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
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unsigned EOP = (std::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
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BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
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.addOperand(MI->getOperand(0))
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.addOperand(MI->getOperand(1))
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.addImm(EOP); // Set End of program bit
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.addImm(isEOP(I)); // Set End of program bit
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break;
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}
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@ -539,7 +541,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
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}
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}
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}
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bool EOP = (std::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
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bool EOP = isEOP(I);
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if (!EOP && !isLastInstructionOfItsType)
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return BB;
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unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
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