parent
fef7dec9cc
commit
c0bf377f98
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@ -27,9 +27,9 @@
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using namespace llvm;
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namespace llvm {
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extern cl::opt<bool> EnableAlphaIDIV;
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extern cl::opt<bool> EnableAlphaCount;
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extern cl::opt<bool> EnableAlphaLSMark;
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cl::opt<bool> EnableAlphaLSMark("enable-alpha-lsmark",
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cl::desc("Emit symbols to correlate Mem ops to LLVM Values"),
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cl::Hidden);
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}
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/// AddLiveIn - This helper function adds the specified physical register to the
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File diff suppressed because it is too large
Load Diff
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@ -28,12 +28,6 @@ namespace {
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RegisterTarget<AlphaTargetMachine> X("alpha", " Alpha (incomplete)");
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}
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namespace llvm {
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cl::opt<bool> DisableAlphaDAG("disable-alpha-dag-isel",
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cl::desc("Disable DAG ISEL for Alpha"),
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cl::Hidden);
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}
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unsigned AlphaTargetMachine::getModuleMatchQuality(const Module &M) {
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// We strongly match "alpha*".
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std::string TT = M.getTargetTriple();
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@ -94,10 +88,7 @@ bool AlphaTargetMachine::addPassesToEmitFile(PassManager &PM,
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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if (!DisableAlphaDAG)
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PM.add(createAlphaISelDag(*this));
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else
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PM.add(createAlphaPatternInstructionSelector(*this));
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PM.add(createAlphaISelDag(*this));
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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@ -135,7 +126,7 @@ void AlphaJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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PM.add(createAlphaPatternInstructionSelector(TM));
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PM.add(createAlphaISelDag(TM));
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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