- Reorg Thumb load / store instructions. Combine each rr and ri pair of
instructions into one (e.g. tLDRrr, tLDRri -> tLDR). - Thumb ldrsb and ldrsh only have the [reg, reg] address format. If the address is not an add, materialize a 0 immediate into a register and use it as the offset field. llvm-svn: 33470
This commit is contained in:
Evan Cheng
parent
40ec08095b
commit
c0b7366cf9
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@ -98,9 +98,9 @@ namespace {
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void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNo);
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void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNo,
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unsigned Scale);
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void printThumbAddrModeRI5_1Operand(const MachineInstr *MI, int OpNo);
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void printThumbAddrModeRI5_2Operand(const MachineInstr *MI, int OpNo);
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void printThumbAddrModeRI5_4Operand(const MachineInstr *MI, int OpNo);
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void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNo);
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void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNo);
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void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNo);
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void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNo);
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void printCCOperand(const MachineInstr *MI, int opNum);
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void printPCLabel(const MachineInstr *MI, int opNum);
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@ -518,7 +518,7 @@ void
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ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
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unsigned Scale) {
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const MachineOperand &MO1 = MI->getOperand(Op);
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const MachineOperand &MO2 = MI->getOperand(Op+1);
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const MachineOperand &MO2 = MI->getOperand(Op+2);
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if (!MO1.isRegister()) { // FIXME: This is for CP entries, but isn't right.
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printOperand(MI, Op);
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@ -535,16 +535,25 @@ ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
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}
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void
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ARMAsmPrinter::printThumbAddrModeRI5_1Operand(const MachineInstr *MI, int Op) {
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printThumbAddrModeRI5Operand(MI, Op, 1);
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ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
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if (MI->getOperand(Op+1).getReg())
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printThumbAddrModeRROperand(MI, Op);
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else
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printThumbAddrModeRI5Operand(MI, Op, 1);
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}
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void
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ARMAsmPrinter::printThumbAddrModeRI5_2Operand(const MachineInstr *MI, int Op) {
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printThumbAddrModeRI5Operand(MI, Op, 2);
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ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
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if (MI->getOperand(Op+1).getReg())
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printThumbAddrModeRROperand(MI, Op);
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else
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printThumbAddrModeRI5Operand(MI, Op, 2);
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}
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void
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ARMAsmPrinter::printThumbAddrModeRI5_4Operand(const MachineInstr *MI, int Op) {
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printThumbAddrModeRI5Operand(MI, Op, 4);
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ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
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if (MI->getOperand(Op+1).getReg())
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printThumbAddrModeRROperand(MI, Op);
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else
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printThumbAddrModeRI5Operand(MI, Op, 4);
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}
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void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
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@ -71,12 +71,12 @@ public:
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bool SelectThumbAddrModeRR(SDOperand Op, SDOperand N, SDOperand &Base,
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SDOperand &Offset);
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bool SelectThumbAddrModeRI5_1(SDOperand Op, SDOperand N, SDOperand &Base,
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SDOperand &Offset);
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bool SelectThumbAddrModeRI5_2(SDOperand Op, SDOperand N, SDOperand &Base,
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SDOperand &Offset);
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bool SelectThumbAddrModeRI5_4(SDOperand Op, SDOperand N, SDOperand &Base,
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SDOperand &Offset);
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bool SelectThumbAddrModeS1(SDOperand Op, SDOperand N, SDOperand &Base,
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SDOperand &Offset, SDOperand &OffImm);
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bool SelectThumbAddrModeS2(SDOperand Op, SDOperand N, SDOperand &Base,
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SDOperand &Offset, SDOperand &OffImm);
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bool SelectThumbAddrModeS4(SDOperand Op, SDOperand N, SDOperand &Base,
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SDOperand &Offset, SDOperand &OffImm);
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bool SelectThumbAddrModeSP(SDOperand Op, SDOperand N, SDOperand &Base,
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SDOperand &Offset);
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@ -340,8 +340,16 @@ bool ARMDAGToDAGISel::SelectAddrModePC(SDOperand Op, SDOperand N,
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bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDOperand Op, SDOperand N,
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SDOperand &Base, SDOperand &Offset){
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if (N.getOpcode() != ISD::ADD)
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return false;
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if (N.getOpcode() != ISD::ADD) {
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Base = N;
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// We must materialize a zero in a reg! Returning an constant here won't
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// work since its node is -1 so it won't get added to the selection queue.
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// Explicitly issue a tMOVri8 node!
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Offset = SDOperand(CurDAG->getTargetNode(ARM::tMOVri8, MVT::i32,
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CurDAG->getTargetConstant(0, MVT::i32)), 0);
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return true;
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}
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Base = N.getOperand(0);
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Offset = N.getOperand(1);
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return true;
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@ -349,13 +357,15 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDOperand Op, SDOperand N,
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static bool SelectThumbAddrModeRI5(SDOperand N, unsigned Scale,
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TargetLowering &TLI, SelectionDAG *CurDAG,
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SDOperand &Base, SDOperand &Offset) {
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SDOperand &Base, SDOperand &Offset,
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SDOperand &OffImm) {
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if (N.getOpcode() == ISD::FrameIndex)
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return false;
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if (N.getOpcode() != ISD::ADD) {
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Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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Offset = CurDAG->getRegister(0, MVT::i32);
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OffImm = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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@ -366,28 +376,35 @@ static bool SelectThumbAddrModeRI5(SDOperand N, unsigned Scale,
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RHSC /= Scale;
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if (RHSC >= 0 && RHSC < 32) {
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Base = N.getOperand(0);
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Offset = CurDAG->getTargetConstant(RHSC, MVT::i32);
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Offset = CurDAG->getRegister(0, MVT::i32);
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OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
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return true;
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}
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}
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}
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return false;
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Base = N.getOperand(0);
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Offset = N.getOperand(1);
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OffImm = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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bool ARMDAGToDAGISel::SelectThumbAddrModeRI5_1(SDOperand Op, SDOperand N,
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SDOperand &Base, SDOperand &Offset){
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return SelectThumbAddrModeRI5(N, 1, TLI, CurDAG, Base, Offset);
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bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDOperand Op, SDOperand N,
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SDOperand &Base, SDOperand &Offset,
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SDOperand &OffImm) {
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return SelectThumbAddrModeRI5(N, 1, TLI, CurDAG, Base, Offset, OffImm);
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}
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bool ARMDAGToDAGISel::SelectThumbAddrModeRI5_2(SDOperand Op, SDOperand N,
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SDOperand &Base, SDOperand &Offset){
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return SelectThumbAddrModeRI5(N, 2, TLI, CurDAG, Base, Offset);
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bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDOperand Op, SDOperand N,
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SDOperand &Base, SDOperand &Offset,
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SDOperand &OffImm) {
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return SelectThumbAddrModeRI5(N, 2, TLI, CurDAG, Base, Offset, OffImm);
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}
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bool ARMDAGToDAGISel::SelectThumbAddrModeRI5_4(SDOperand Op, SDOperand N,
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SDOperand &Base, SDOperand &Offset){
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return SelectThumbAddrModeRI5(N, 4, TLI, CurDAG, Base, Offset);
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bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDOperand Op, SDOperand N,
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SDOperand &Base, SDOperand &Offset,
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SDOperand &OffImm) {
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return SelectThumbAddrModeRI5(N, 4, TLI, CurDAG, Base, Offset, OffImm);
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}
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bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDOperand Op, SDOperand N,
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@ -114,22 +114,31 @@ def t_addrmode_rr : Operand<i32>,
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let MIOperandInfo = (ops GPR:$base, GPR:$offsreg);
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}
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// t_addrmode_ri5_{1|2|4} := reg + imm5 * {1|2|4}
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// t_addrmode_s4 := reg + reg
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// reg + imm5 * 4
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//
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def t_addrmode_ri5_1 : Operand<i32>,
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ComplexPattern<i32, 2, "SelectThumbAddrModeRI5_1", []> {
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let PrintMethod = "printThumbAddrModeRI5_1Operand";
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
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def t_addrmode_s4 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
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let PrintMethod = "printThumbAddrModeS4Operand";
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let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
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}
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def t_addrmode_ri5_2 : Operand<i32>,
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ComplexPattern<i32, 2, "SelectThumbAddrModeRI5_2", []> {
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let PrintMethod = "printThumbAddrModeRI5_2Operand";
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
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// t_addrmode_s2 := reg + reg
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// reg + imm5 * 2
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//
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def t_addrmode_s2 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
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let PrintMethod = "printThumbAddrModeS2Operand";
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let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
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}
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def t_addrmode_ri5_4 : Operand<i32>,
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ComplexPattern<i32, 2, "SelectThumbAddrModeRI5_4", []> {
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let PrintMethod = "printThumbAddrModeRI5_4Operand";
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
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// t_addrmode_s1 := reg + reg
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// reg + imm5
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//
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def t_addrmode_s1 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
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let PrintMethod = "printThumbAddrModeS1Operand";
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let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
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}
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// t_addrmode_sp := sp + imm8 * 4
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@ -191,71 +200,48 @@ let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in
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//
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let isLoad = 1 in {
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def tLDRri : TI4<(ops GPR:$dst, t_addrmode_ri5_4:$addr),
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"ldr $dst, $addr",
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[(set GPR:$dst, (load t_addrmode_ri5_4:$addr))]>;
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def tLDR : TI4<(ops GPR:$dst, t_addrmode_s4:$addr),
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"ldr $dst, $addr",
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[(set GPR:$dst, (load t_addrmode_s4:$addr))]>;
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def tLDRB : TI1<(ops GPR:$dst, t_addrmode_s1:$addr),
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"ldrb $dst, $addr",
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[(set GPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
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def tLDRH : TI2<(ops GPR:$dst, t_addrmode_s2:$addr),
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"ldrh $dst, $addr",
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[(set GPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
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def tLDRSB : TI1<(ops GPR:$dst, t_addrmode_rr:$addr),
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"ldrsb $dst, $addr",
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[(set GPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
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def tLDRSH : TI2<(ops GPR:$dst, t_addrmode_rr:$addr),
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"ldrsh $dst, $addr",
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[(set GPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
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def tLDRrr : TI<(ops GPR:$dst, t_addrmode_rr:$addr),
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"ldr $dst, $addr",
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[(set GPR:$dst, (load t_addrmode_rr:$addr))]>;
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// def tLDRpci
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def tLDRspi : TIs<(ops GPR:$dst, t_addrmode_sp:$addr),
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"ldr $dst, $addr",
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[(set GPR:$dst, (load t_addrmode_sp:$addr))]>;
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def tLDRBri : TI1<(ops GPR:$dst, t_addrmode_ri5_1:$addr),
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"ldrb $dst, $addr",
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[(set GPR:$dst, (zextloadi8 t_addrmode_ri5_1:$addr))]>;
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def tLDRBrr : TI1<(ops GPR:$dst, t_addrmode_rr:$addr),
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"ldrb $dst, $addr",
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[(set GPR:$dst, (zextloadi8 t_addrmode_rr:$addr))]>;
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def tLDRHri : TI2<(ops GPR:$dst, t_addrmode_ri5_2:$addr),
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"ldrh $dst, $addr",
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[(set GPR:$dst, (zextloadi16 t_addrmode_ri5_2:$addr))]>;
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def tLDRHrr : TI2<(ops GPR:$dst, t_addrmode_rr:$addr),
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"ldrh $dst, $addr",
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[(set GPR:$dst, (zextloadi16 t_addrmode_rr:$addr))]>;
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def tLDRSBrr : TI1<(ops GPR:$dst, t_addrmode_rr:$addr),
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"ldrsb $dst, $addr",
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[(set GPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
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def tLDRSHrr : TI2<(ops GPR:$dst, t_addrmode_rr:$addr),
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"ldrsh $dst, $addr",
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[(set GPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
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} // isLoad
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let isStore = 1 in {
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def tSTRri : TI4<(ops GPR:$src, t_addrmode_ri5_4:$addr),
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"str $src, $addr",
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[(store GPR:$src, t_addrmode_ri5_4:$addr)]>;
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def tSTR : TI4<(ops GPR:$src, t_addrmode_s4:$addr),
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"str $src, $addr",
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[(store GPR:$src, t_addrmode_s4:$addr)]>;
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def tSTRrr : TI<(ops GPR:$src, t_addrmode_rr:$addr),
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"str $src, $addr",
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[(store GPR:$src, t_addrmode_rr:$addr)]>;
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def tSTRB : TI1<(ops GPR:$src, t_addrmode_s1:$addr),
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"strb $src, $addr",
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[(truncstorei8 GPR:$src, t_addrmode_s1:$addr)]>;
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def tSTRH : TI2<(ops GPR:$src, t_addrmode_s2:$addr),
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"strh $src, $addr",
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[(truncstorei16 GPR:$src, t_addrmode_s2:$addr)]>;
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def tSTRspi : TIs<(ops GPR:$src, t_addrmode_sp:$addr),
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"str $src, $addr",
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[(store GPR:$src, t_addrmode_sp:$addr)]>;
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def tSTRBri : TI1<(ops GPR:$src, t_addrmode_ri5_1:$addr),
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"strb $src, $addr",
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[(truncstorei8 GPR:$src, t_addrmode_ri5_1:$addr)]>;
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def tSTRBrr : TI1<(ops GPR:$src, t_addrmode_rr:$addr),
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"strb $src, $addr",
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[(truncstorei8 GPR:$src, t_addrmode_rr:$addr)]>;
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def tSTRHri : TI2<(ops GPR:$src, t_addrmode_ri5_2:$addr),
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"strh $src, $addr",
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[(truncstorei16 GPR:$src, t_addrmode_ri5_1:$addr)]>;
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def tSTRHrr : TI2<(ops GPR:$src, t_addrmode_rr:$addr),
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"strh $src, $addr",
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[(truncstorei16 GPR:$src, t_addrmode_rr:$addr)]>;
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}
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//===----------------------------------------------------------------------===//
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@ -491,16 +477,12 @@ def : ThumbV5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>;
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def : ThumbV5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>;
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// zextload i1 -> zextload i8
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def : ThumbPat<(zextloadi1 t_addrmode_ri5_1:$addr),
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(tLDRBri t_addrmode_ri5_1:$addr)>;
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def : ThumbPat<(zextloadi1 t_addrmode_rr:$addr),
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(tLDRBri t_addrmode_rr:$addr)>;
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def : ThumbPat<(zextloadi1 t_addrmode_s1:$addr),
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(tLDRB t_addrmode_s1:$addr)>;
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// truncstore i1 -> truncstore i8
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def : ThumbPat<(truncstorei1 GPR:$src, t_addrmode_ri5_1:$dst),
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(tSTRBri GPR:$src, t_addrmode_ri5_1:$dst)>;
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def : ThumbPat<(truncstorei1 GPR:$src, t_addrmode_rr:$dst),
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(tSTRBrr GPR:$src, t_addrmode_rr:$dst)>;
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def : ThumbPat<(truncstorei1 GPR:$src, t_addrmode_s1:$dst),
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(tSTRB GPR:$src, t_addrmode_s1:$dst)>;
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// Large immediate handling.
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