[globalisel][aarch64] Prefix PartialMappingIdx enumerators with 'PMI_' to fit coding standards.
This also stops things like 'None' polluting the llvm::AArch64 namespace. llvm-svn: 288799
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@ -26,18 +26,18 @@ RegisterBank *RegBanks[] = {&GPRRegBank, &FPRRegBank, &CCRRegBank};
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// PartialMappings.
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enum PartialMappingIdx {
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None = -1,
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GPR32 = 0,
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GPR64,
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FPR32,
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FPR64,
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FPR128,
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FPR256,
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FPR512,
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FirstGPR = GPR32,
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LastGPR = GPR64,
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FirstFPR = FPR32,
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LastFPR = FPR512
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PMI_None = -1,
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PMI_GPR32 = 0,
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PMI_GPR64,
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PMI_FPR32,
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PMI_FPR64,
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PMI_FPR128,
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PMI_FPR256,
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PMI_FPR512,
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PMI_FirstGPR = PMI_GPR32,
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PMI_LastGPR = PMI_GPR64,
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PMI_FirstFPR = PMI_FPR32,
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PMI_LastFPR = PMI_FPR512
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};
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static unsigned getRegBankBaseIdxOffset(unsigned Size) {
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@ -115,7 +115,7 @@ RegisterBankInfo::ValueMapping ValMappings[] {
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/// \pre \p RBIdx != PartialMappingIdx::None
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const RegisterBankInfo::ValueMapping *
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getValueMapping(PartialMappingIdx RBIdx, unsigned Size) {
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assert(RBIdx != PartialMappingIdx::None && "No mapping needed for that");
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assert(RBIdx != PartialMappingIdx::PMI_None && "No mapping needed for that");
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unsigned ValMappingIdx = First3OpsIdx +
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(RBIdx + getRegBankBaseIdxOffset(Size)) *
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ValueMappingIdx::DistanceBetweenRegBanks;
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@ -133,14 +133,14 @@ getValueMapping(PartialMappingIdx RBIdx, unsigned Size) {
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/// otherwise it is on FPR. Same thing for \p SrcIsGPR.
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const RegisterBankInfo::ValueMapping *
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getCopyMapping(bool DstIsGPR, bool SrcIsGPR, unsigned Size) {
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PartialMappingIdx DstRBIdx = DstIsGPR ? FirstGPR : FirstFPR;
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PartialMappingIdx SrcRBIdx = SrcIsGPR ? FirstGPR : FirstFPR;
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PartialMappingIdx DstRBIdx = DstIsGPR ? PMI_FirstGPR : PMI_FirstFPR;
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PartialMappingIdx SrcRBIdx = SrcIsGPR ? PMI_FirstGPR : PMI_FirstFPR;
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if (DstRBIdx == SrcRBIdx)
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return getValueMapping(DstRBIdx, Size);
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assert(Size <= 64 && "GPR cannot handle that size");
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unsigned ValMappingIdx =
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FirstCrossRegCpyIdx +
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(DstRBIdx - FirstGPR + getRegBankBaseIdxOffset(Size)) *
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(DstRBIdx - PMI_FirstGPR + getRegBankBaseIdxOffset(Size)) *
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ValueMappingIdx::DistanceBetweenCrossRegCpy;
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assert(ValMappingIdx >= AArch64::FirstCrossRegCpyIdx &&
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ValMappingIdx <= AArch64::LastCrossRegCpyIdx &&
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@ -83,32 +83,32 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
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// Check that the TableGen'ed like file is in sync we our expectations.
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// First, the Idx.
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assert(AArch64::PartialMappingIdx::GPR32 ==
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AArch64::PartialMappingIdx::FirstGPR &&
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assert(AArch64::PartialMappingIdx::PMI_GPR32 ==
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AArch64::PartialMappingIdx::PMI_FirstGPR &&
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"GPR32 index not first in the GPR list");
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assert(AArch64::PartialMappingIdx::GPR64 ==
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AArch64::PartialMappingIdx::LastGPR &&
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assert(AArch64::PartialMappingIdx::PMI_GPR64 ==
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AArch64::PartialMappingIdx::PMI_LastGPR &&
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"GPR64 index not last in the GPR list");
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assert(AArch64::PartialMappingIdx::FirstGPR <=
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AArch64::PartialMappingIdx::LastGPR &&
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assert(AArch64::PartialMappingIdx::PMI_FirstGPR <=
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AArch64::PartialMappingIdx::PMI_LastGPR &&
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"GPR list is backward");
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assert(AArch64::PartialMappingIdx::FPR32 ==
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AArch64::PartialMappingIdx::FirstFPR &&
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assert(AArch64::PartialMappingIdx::PMI_FPR32 ==
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AArch64::PartialMappingIdx::PMI_FirstFPR &&
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"FPR32 index not first in the FPR list");
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assert(AArch64::PartialMappingIdx::FPR512 ==
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AArch64::PartialMappingIdx::LastFPR &&
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assert(AArch64::PartialMappingIdx::PMI_FPR512 ==
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AArch64::PartialMappingIdx::PMI_LastFPR &&
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"FPR512 index not last in the FPR list");
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assert(AArch64::PartialMappingIdx::FirstFPR <=
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AArch64::PartialMappingIdx::LastFPR &&
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assert(AArch64::PartialMappingIdx::PMI_FirstFPR <=
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AArch64::PartialMappingIdx::PMI_LastFPR &&
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"FPR list is backward");
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assert(AArch64::PartialMappingIdx::FPR32 + 1 ==
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AArch64::PartialMappingIdx::FPR64 &&
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AArch64::PartialMappingIdx::FPR64 + 1 ==
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AArch64::PartialMappingIdx::FPR128 &&
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AArch64::PartialMappingIdx::FPR128 + 1 ==
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AArch64::PartialMappingIdx::FPR256 &&
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AArch64::PartialMappingIdx::FPR256 + 1 ==
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AArch64::PartialMappingIdx::FPR512 &&
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assert(AArch64::PartialMappingIdx::PMI_FPR32 + 1 ==
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AArch64::PartialMappingIdx::PMI_FPR64 &&
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AArch64::PartialMappingIdx::PMI_FPR64 + 1 ==
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AArch64::PartialMappingIdx::PMI_FPR128 &&
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AArch64::PartialMappingIdx::PMI_FPR128 + 1 ==
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AArch64::PartialMappingIdx::PMI_FPR256 &&
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AArch64::PartialMappingIdx::PMI_FPR256 + 1 ==
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AArch64::PartialMappingIdx::PMI_FPR512 &&
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"FPR indices not properly ordered");
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// Now, the content.
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// Check partial mapping.
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@ -121,22 +121,22 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
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Map.RegBank == &RB && #Idx " is incorrectly initialized"); \
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} while (0)
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CHECK_PARTIALMAP(GPR32, 0, 32, RBGPR);
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CHECK_PARTIALMAP(GPR64, 0, 64, RBGPR);
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CHECK_PARTIALMAP(FPR32, 0, 32, RBFPR);
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CHECK_PARTIALMAP(FPR64, 0, 64, RBFPR);
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CHECK_PARTIALMAP(FPR128, 0, 128, RBFPR);
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CHECK_PARTIALMAP(FPR256, 0, 256, RBFPR);
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CHECK_PARTIALMAP(FPR512, 0, 512, RBFPR);
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CHECK_PARTIALMAP(PMI_GPR32, 0, 32, RBGPR);
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CHECK_PARTIALMAP(PMI_GPR64, 0, 64, RBGPR);
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CHECK_PARTIALMAP(PMI_FPR32, 0, 32, RBFPR);
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CHECK_PARTIALMAP(PMI_FPR64, 0, 64, RBFPR);
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CHECK_PARTIALMAP(PMI_FPR128, 0, 128, RBFPR);
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CHECK_PARTIALMAP(PMI_FPR256, 0, 256, RBFPR);
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CHECK_PARTIALMAP(PMI_FPR512, 0, 512, RBFPR);
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// Check value mapping.
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#define CHECK_VALUEMAP_IMPL(RBName, Size, Offset) \
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do { \
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AArch64::PartialMappingIdx PartialMapBaseIdx = \
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AArch64::PartialMappingIdx::RBName##Size; \
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AArch64::PartialMappingIdx::PMI_##RBName##Size; \
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(void) PartialMapBaseIdx; \
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const ValueMapping &Map = \
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AArch64::getValueMapping(AArch64::First##RBName, Size)[Offset]; \
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AArch64::getValueMapping(AArch64::PMI_First##RBName, Size)[Offset]; \
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(void) Map; \
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assert(Map.BreakDown == &AArch64::PartMappings[PartialMapBaseIdx] && \
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Map.NumBreakDowns == 1 && #RBName #Size \
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@ -173,14 +173,14 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
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#define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size) \
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do { \
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AArch64::PartialMappingIdx PartialMapDstIdx = \
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AArch64::PartialMappingIdx::RBNameDst##Size; \
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AArch64::PartialMappingIdx::PMI_##RBNameDst##Size; \
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AArch64::PartialMappingIdx PartialMapSrcIdx = \
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AArch64::PartialMappingIdx::RBNameSrc##Size; \
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AArch64::PartialMappingIdx::PMI_##RBNameSrc##Size; \
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(void) PartialMapDstIdx; \
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(void) PartialMapSrcIdx; \
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const ValueMapping *Map = AArch64::getCopyMapping( \
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AArch64::First##RBNameDst == AArch64::FirstGPR, \
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AArch64::First##RBNameSrc == AArch64::FirstGPR, Size); \
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AArch64::PMI_First##RBNameDst == AArch64::PMI_FirstGPR, \
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AArch64::PMI_First##RBNameSrc == AArch64::PMI_FirstGPR, Size); \
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(void) Map; \
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assert(Map[0].BreakDown == &AArch64::PartMappings[PartialMapDstIdx] && \
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Map[0].NumBreakDowns == 1 && #RBNameDst #Size \
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@ -283,10 +283,12 @@ AArch64RegisterBankInfo::getInstrAlternativeMappings(
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break;
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InstructionMappings AltMappings;
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InstructionMapping GPRMapping(
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/*ID*/ 1, /*Cost*/ 1, AArch64::getValueMapping(AArch64::FirstGPR, Size),
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/*ID*/ 1, /*Cost*/ 1,
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AArch64::getValueMapping(AArch64::PMI_FirstGPR, Size),
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/*NumOperands*/ 3);
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InstructionMapping FPRMapping(
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/*ID*/ 2, /*Cost*/ 1, AArch64::getValueMapping(AArch64::FirstFPR, Size),
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/*ID*/ 2, /*Cost*/ 1,
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AArch64::getValueMapping(AArch64::PMI_FirstFPR, Size),
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/*NumOperands*/ 3);
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AltMappings.emplace_back(std::move(GPRMapping));
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@ -342,15 +344,17 @@ AArch64RegisterBankInfo::getInstrAlternativeMappings(
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InstructionMappings AltMappings;
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InstructionMapping GPRMapping(
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/*ID*/ 1, /*Cost*/ 1,
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getOperandsMapping({AArch64::getValueMapping(AArch64::FirstGPR, Size),
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// Addresses are GPR 64-bit.
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AArch64::getValueMapping(AArch64::FirstGPR, 64)}),
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getOperandsMapping(
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{AArch64::getValueMapping(AArch64::PMI_FirstGPR, Size),
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// Addresses are GPR 64-bit.
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AArch64::getValueMapping(AArch64::PMI_FirstGPR, 64)}),
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/*NumOperands*/ 2);
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InstructionMapping FPRMapping(
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/*ID*/ 2, /*Cost*/ 1,
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getOperandsMapping({AArch64::getValueMapping(AArch64::FirstFPR, Size),
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// Addresses are GPR 64-bit.
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AArch64::getValueMapping(AArch64::FirstGPR, 64)}),
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getOperandsMapping(
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{AArch64::getValueMapping(AArch64::PMI_FirstFPR, Size),
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// Addresses are GPR 64-bit.
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AArch64::getValueMapping(AArch64::PMI_FirstGPR, 64)}),
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/*NumOperands*/ 2);
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AltMappings.emplace_back(std::move(GPRMapping));
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@ -431,7 +435,7 @@ AArch64RegisterBankInfo::getSameKindOfOperandsMapping(const MachineInstr &MI) {
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#endif // End NDEBUG.
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AArch64::PartialMappingIdx RBIdx =
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IsFPR ? AArch64::FirstFPR : AArch64::FirstGPR;
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IsFPR ? AArch64::PMI_FirstFPR : AArch64::PMI_FirstGPR;
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return InstructionMapping{DefaultMappingID, 1,
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AArch64::getValueMapping(RBIdx, Size), NumOperands};
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@ -508,9 +512,9 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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// As a top-level guess, vectors go in FPRs, scalars and pointers in GPRs.
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// For floating-point instructions, scalars go in FPRs.
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if (Ty.isVector() || isPreISelGenericFloatingPointOpcode(Opc))
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OpRegBankIdx[Idx] = AArch64::FirstFPR;
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OpRegBankIdx[Idx] = AArch64::PMI_FirstFPR;
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else
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OpRegBankIdx[Idx] = AArch64::FirstGPR;
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OpRegBankIdx[Idx] = AArch64::PMI_FirstGPR;
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}
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unsigned Cost = 1;
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@ -519,18 +523,18 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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switch (Opc) {
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case TargetOpcode::G_SITOFP:
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case TargetOpcode::G_UITOFP: {
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OpRegBankIdx = {AArch64::FirstFPR, AArch64::FirstGPR};
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OpRegBankIdx = {AArch64::PMI_FirstFPR, AArch64::PMI_FirstGPR};
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break;
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}
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case TargetOpcode::G_FPTOSI:
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case TargetOpcode::G_FPTOUI: {
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OpRegBankIdx = {AArch64::FirstGPR, AArch64::FirstFPR};
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OpRegBankIdx = {AArch64::PMI_FirstGPR, AArch64::PMI_FirstFPR};
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break;
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}
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case TargetOpcode::G_FCMP: {
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OpRegBankIdx = {AArch64::FirstGPR,
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/* Predicate */ AArch64::PartialMappingIdx::None,
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AArch64::FirstFPR, AArch64::FirstFPR};
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OpRegBankIdx = {AArch64::PMI_FirstGPR,
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/* Predicate */ AArch64::PMI_None, AArch64::PMI_FirstFPR,
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AArch64::PMI_FirstFPR};
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break;
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}
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case TargetOpcode::G_BITCAST: {
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@ -548,7 +552,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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// for the greedy mode the cost of the cross bank copy will
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// offset this number.
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// FIXME: Should be derived from the scheduling model.
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if (OpRegBankIdx[0] >= AArch64::FirstFPR)
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if (OpRegBankIdx[0] >= AArch64::PMI_FirstFPR)
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Cost = 2;
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}
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}
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