Avoid -Wunused-variable in -asserts builds
llvm-svn: 128048
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@ -607,11 +607,6 @@ static bool DisassembleThumb1LdSt(unsigned opA, MCInst &MI, unsigned Opcode,
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const TargetOperandInfo *OpInfo = TID.OpInfo;
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const TargetOperandInfo *OpInfo = TID.OpInfo;
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unsigned &OpIdx = NumOpsAdded;
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unsigned &OpIdx = NumOpsAdded;
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// Table A6-5 16-bit Thumb Load/store instructions
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// opA = 0b0101 for STR/LDR (register) and friends.
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// Otherwise, we have STR/LDR (immediate) and friends.
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bool Imm5 = (opA != 5);
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assert(NumOps >= 2
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assert(NumOps >= 2
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&& OpInfo[0].RegClass == ARM::tGPRRegClassID
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&& OpInfo[0].RegClass == ARM::tGPRRegClassID
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&& OpInfo[1].RegClass == ARM::tGPRRegClassID
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&& OpInfo[1].RegClass == ARM::tGPRRegClassID
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@ -632,7 +627,10 @@ static bool DisassembleThumb1LdSt(unsigned opA, MCInst &MI, unsigned Opcode,
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if (OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() &&
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if (OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() &&
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!OpInfo[OpIdx].isOptionalDef()) {
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!OpInfo[OpIdx].isOptionalDef()) {
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assert(Imm5 && "Immediate operand expected for this opcode");
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// Table A6-5 16-bit Thumb Load/store instructions
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// opA = 0b0101 for STR/LDR (register) and friends.
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// Otherwise, we have STR/LDR (immediate) and friends.
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assert(opA != 5 && "Immediate operand expected for this opcode");
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MI.addOperand(MCOperand::CreateImm(getT1Imm5(insn)));
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MI.addOperand(MCOperand::CreateImm(getT1Imm5(insn)));
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++OpIdx;
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++OpIdx;
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} else {
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} else {
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