diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 15a57c5a83df..4cf5acce849b 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -53,7 +53,9 @@ def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
                                "!ADJCALLSTACKDOWN $amt",
                                [(callseq_start imm:$amt)]>;
 
-def bxr: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
+let isReturn = 1 in {
+  def bx: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
+}
 
 def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
 
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
index e7e1690596fe..8daf06579489 100644
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -116,10 +116,30 @@ void ARMRegisterInfo::
 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
 
 void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
+  MachineBasicBlock &MBB = MF.front();
+  MachineFrameInfo  *MFI = MF.getFrameInfo();
+  int           NumBytes = (int) MFI->getStackSize();
+
+  //hack
+  assert(NumBytes == 0);
+
+  //add a sp = sp - 4
+  BuildMI(MBB, MBB.begin(), ARM::str, 1, ARM::R14).addReg(ARM::R13);
 }
 
 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
 				   MachineBasicBlock &MBB) const {
+  MachineBasicBlock::iterator MBBI = prior(MBB.end());
+  assert(MBBI->getOpcode() == ARM::bx &&
+         "Can only insert epilog into returning blocks");
+
+  MachineFrameInfo *MFI = MF.getFrameInfo();
+  int          NumBytes = (int) MFI->getStackSize();
+  //hack
+  assert(NumBytes == 0);
+
+  BuildMI(MBB, MBBI, ARM::ldr, 2, ARM::R14).addImm(0).addReg(ARM::R13);
+  //add a sp = sp + 4
 }
 
 unsigned ARMRegisterInfo::getRARegister() const {