checkpoint, don't expect this to read right yet. :)
llvm-svn: 115426
This commit is contained in:
Chris Lattner
parent
4e3918c06b
commit
bf1cf670a6
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@ -67,7 +67,6 @@ current one. To see the release notes for a specific release, please see the
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Almost dead code.
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include/llvm/Analysis/LiveValues.h => Dan
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lib/Transforms/IPO/MergeFunctions.cpp => consider for 2.8.
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llvm/Analysis/PointerTracking.h => Edwin wants this, consider for 2.8.
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GEPSplitterPass
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-->
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@ -82,79 +81,6 @@ Almost dead code.
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<!-- Announcement, lldb, libc++ -->
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<!-- to write:
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MachineCSE tuned and on by default.
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llvm.dbg.value: variable debug info for optimized code
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MC Assembler backend is now real, does relaxation and is bitwise identical
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with darwin assembler in huge majority of all cases.
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new GHC calling convention
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New half float intrinsics LangRef.html#int_fp16
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Rewrote tblgen's type inference for backends to be more consistent and
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diagnose more target bugs. This also allows limited support for writing
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patterns for instructions that return multiple results, e.g. a virtual
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register and a flag result. Stuff that used 'parallel' before should use
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this.
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New ARM/Thumb disassembler support in MC.
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New SSEDomainFix pass:
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On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a
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register in a different domain than where it was defined. Some instructions
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have equvivalents for different domains, like por/orps/orpd. The
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SSEDomainFix pass tries to minimize the number of domain crossings by
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changing between equvivalent opcodes where possible.
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Support for the Intel AES instructions in the assembler.
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memcpy, memmove, and memset now take address space qualified pointers + volatile.
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per-instruction debug info metadata is much faster and uses less space (new DebugLoc class).
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-ffunction-sections and -fdata-sections are supported on ELF targets.
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Now iterate function passes when a cgsccpassmanager detects a devirtualization
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-momit-leaf-frame-pointer now supported.
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New -regalloc=fast, =local got removed
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New -regalloc=default option that chooses a register allocator based on the -O optimization level.
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New "trap values" concept: http://llvm.org/docs/LangRef.html#trapvalues
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Improved trip count analysis for <= and >= loops, and uses sign overflow info.
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REMOVED: SCCVN pass.
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X86 backend attempts to promote 16-bit integer operations to 32-bits to avoid
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0x66 prefixes, which are slow on some microarchitectures and bloat the code
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on others.
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X87 fp stackifier is global!
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LTO debug info support?
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NEON: Better performance for QQQQ (4-consecutive Q register) instructions. New reg sequence abstraction?
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New support for X86 "thiscall" calling convention (x86_thiscallcc in IR).
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ARM: Better scheduling (list-hybrid, hybrid?)
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New SubRegIndex tblgen class for targets -> jakob
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ARM: Tail call support.
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AVX support in the MC assembler. Full compiler support not done yet.
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Atomics now get legalized when not natively supported (jim g)
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ARM: General performance work and tuning.
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Bottom up fast isel. Simple Load reuse. No more machinedce. Load folding at -O0?
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New linker_private_weak and linker_private_weak_def_auto linkage types
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compiler_rt softfloat support.
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X86 ABI: <2 x float> in IR no longer maps onto MMX, it turns into <4 x float>
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IR ABI: <3 x float> is passed as <4 x float> instead of 3 floats.
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renamed "Release" -> "Release+Asserts"; "Release-Asserts" -> "Release etc.
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New COPY instruction. copyRegToReg -> copyPhysReg, isMoveInstr is gone.
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JumpThreading much more aggressive about implied value relations.
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New RegionInfo pass "opt -regions analyze" or "opt -view-regions".
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mc assembler supports macros.
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RenderMachineFunction: -rendermf
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SplitKit?
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Evan: Teach bottom up pre-ra scheduler to track register pressure. Work in progress.
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Evan: Add an ILP scheduler. On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2 by 16%.
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RegisterPass<> -> INTIALIZE_PASS()
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llvm-diff?
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Preliminary work on TBAA but not usable in 2.8.
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Atomic lowering patch: -loweratomic (see Passes.html#loweratomic)
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compiler_rt now includes extensive a fairly testsuite for blocks language feature and the blocks runtime.
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New OptimizeExts+OptimizeCmps -> PeepholeOptimizer pass
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Triples are now stored in normalized form. Triple::normalize.
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New LocalStackSlotAllocation.cpp pass (jimg)
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New llvm.x86.int intrinsic (for int $42 and int3)
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New CorrelatedValuePropagation pass, not on by default in 2.8 yet.
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Verbose assembly decodes X86 shuffle instructions, e.g.:
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insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
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unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
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-->
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<!-- *********************************************************************** -->
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<div class="doc_section">
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@ -253,10 +179,10 @@ libgcc routines).</p>
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<p>
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All of the code in the compiler-rt project is available under the standard LLVM
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License, a "BSD-style" license. New in LLVM 2.8:
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Soft float support
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</p>
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License, a "BSD-style" license. New in LLVM 2.8, compiler_rt now supports
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soft floating point (for targets that don't have a real floating point unit),
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and includes an extensive testsuite for the "blocks" language feature and the
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blocks runtime included in compiler_rt.</p>
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</div>
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@ -526,10 +452,6 @@ organization changes have happened:
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<p>LLVM 2.8 includes several major new capabilities:</p>
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<ul>
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<li>atomic lowering pass.</li>
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<li>RegionInfo pass: opt -regions analyze" or "opt -view-regions".
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<!-- Tobias Grosser --></li>
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<li>ARMGlobalMerge: <!-- Anton --> </li>
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<li>llvm-diff</li>
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</ul>
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@ -546,6 +468,13 @@ expose new optimization opportunities:</p>
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<ul>
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memcpy, memmove, and memset now take address space qualified pointers + volatile.
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per-instruction debug info metadata is much faster and uses less space (new DebugLoc class).
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New "trap values" concept: http://llvm.org/docs/LangRef.html#trapvalues
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New linker_private_weak and linker_private_weak_def_auto linkage types
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Triples are now stored in normalized form. Triple::normalize.
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<li>LLVM 2.8 changes the internal order of operands in <a
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href="http://llvm.org/doxygen/classllvm_1_1InvokeInst.html"><tt>InvokeInst</tt></a>
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and <a href="http://llvm.org/doxygen/classllvm_1_1CallInst.html"><tt>CallInst</tt></a>.
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@ -612,6 +541,14 @@ release includes a few major enhancements and additions to the optimizers:</p>
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<ul>
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<li></li>
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Preliminary work on TBAA but not usable in 2.8.
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New CorrelatedValuePropagation pass, not on by default in 2.8 yet.
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JumpThreading much more aggressive about implied value relations.
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New RegionInfo pass "opt -regions analyze" or "opt -view-regions".
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Improved trip count analysis for <= and >= loops, and uses sign overflow info.
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llvm.dbg.value: variable debug info for optimized code
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Now iterate function passes when a cgsccpassmanager detects a devirtualization
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Atomic lowering patch: -loweratomic (see Passes.html#loweratomic)
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</ul>
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@ -639,22 +576,38 @@ release includes a few major enhancements and additions to the optimizers:</p>
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<div class="doc_text">
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<p>
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FIXME: Rewrite.
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The LLVM Machine Code (aka MC) sub-project of LLVM was created to solve a number
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The LLVM Machine Code (aka MC) subsystem was created to solve a number
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of problems in the realm of assembly, disassembly, object file format handling,
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and a number of other related areas that CPU instruction-set level tools work
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in. It is a sub-project of LLVM which provides it with a number of advantages
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over other compilers that do not have tightly integrated assembly-level tools.
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For a gentle introduction, please see the <a
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in.</p>
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<p>The MC subproject has made great leaps in LLVM 2.8. For example, support for
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directly writing .o files from LLC (and clang) now works reliably for
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darwin/x86[-64] (including inline assembly support) and the integrated
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assembler is turned on by default in Clang for these targets. This provides
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improved compile times among other things.</p>
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<ul>
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<li>The entire compiler has converted over to using the MCStreamer assembler API
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instead of writing out a .s file textually.</li>
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<li>The "assembler parser" is far more mature than in 2.7, supporting a full
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complement of directives, now supports assembler macros, etc.</li>
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<li>The "assembler backend" has been completed, including support for relaxation
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relocation processing and all the other things that an assembler does.</li>
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<li>The MachO file format support is now fully functional and works.</li>
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<li>The MC disassembler now fully supports ARM and Thumb. ARM assembler support
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is still in early development though.</li>
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<li>The X86 MC assembler now supports the X86 AES and AVX instruction set.</li>
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<li>Work on ELF and COFF support is well underway, but isn't useful yet in LLVM
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2.8. Please contact the llvmdev mailing list if you're interested in
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this.</li>
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</ul>
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<p>For more information, please see the <a
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href="http://blog.llvm.org/2010/04/intro-to-llvm-mc-project.html">Intro to the
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LLVM MC Project Blog Post</a>.
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</p>
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<p>2.8 status here. Basic correctness, some obscure missing instructions on
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mainline, on by default in clang.
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Entire compiler backend converted to use mcstreamer.
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</p>
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</div>
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@ -671,7 +624,36 @@ infrastructure, which allows us to implement more aggressive algorithms and make
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it run faster:</p>
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<ul>
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<li>MachO writer works.</li>
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<li></li>
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MachineCSE tuned and on by default.
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Rewrote tblgen's type inference for backends to be more consistent and
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diagnose more target bugs. This also allows limited support for writing
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patterns for instructions that return multiple results, e.g. a virtual
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register and a flag result. Stuff that used 'parallel' before should use
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this.
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New -regalloc=fast, =local got removed
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New -regalloc=default option that chooses a register allocator based on the -O optimization level.
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New SubRegIndex tblgen class for targets -> jakob
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Bottom up fast isel. Simple Load reuse. No more machinedce.
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IR ABI: <3 x float> is passed as <4 x float> instead of 3 floats.
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New COPY instruction. copyRegToReg -> copyPhysReg, isMoveInstr is gone.
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RenderMachineFunction: -rendermf
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SplitKit?
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Evan: Teach bottom up pre-ra scheduler to track register pressure. Work in progress.
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Evan: Add an ILP scheduler. On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2 by 16%.
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New OptimizeExts+OptimizeCmps -> PeepholeOptimizer pass
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New LocalStackSlotAllocation.cpp pass (jimg)
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Atomics now get legalized when not natively supported (jim g)
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-ffunction-sections and -fdata-sections are supported on ELF targets.
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-momit-leaf-frame-pointer now supported.
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</ul>
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</div>
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@ -689,6 +671,30 @@ it run faster:</p>
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in registers across basic blocks, dramatically improving performance of code
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that uses long double, and when targetting CPUs that don't support SSE.</li>
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New SSEDomainFix pass:
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On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a
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register in a different domain than where it was defined. Some instructions
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have equvivalents for different domains, like por/orps/orpd. The
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SSEDomainFix pass tries to minimize the number of domain crossings by
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changing between equvivalent opcodes where possible.
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X86 backend attempts to promote 16-bit integer operations to 32-bits to avoid
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0x66 prefixes, which are slow on some microarchitectures and bloat the code
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on others.
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New support for X86 "thiscall" calling convention (x86_thiscallcc in IR) for windows.
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New llvm.x86.int intrinsic (for int $42 and int3)
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Verbose assembly decodes X86 shuffle instructions, e.g.:
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insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
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unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
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X86 ABI: <2 x float> in IR no longer maps onto MMX, it turns into <4 x float>
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new GHC calling convention
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</ul>
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</div>
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@ -704,6 +710,14 @@ it run faster:</p>
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<ul>
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NEON: Better performance for QQQQ (4-consecutive Q register) instructions. New reg sequence abstraction?
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ARM: Better scheduling (list-hybrid, hybrid?)
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ARM: Tail call support.
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ARM: General performance work and tuning.
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ARM: Half float support through intrinsics LangRef.html#int_fp16
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<li>ARMGlobalMerge: <!-- Anton --> </li>
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<li>
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All of the NEON load and store intrinsics (llvm.arm.neon.vld* and
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llvm.arm.neon.vst*) take an extra parameter to specify the alignment in bytes
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@ -795,17 +809,22 @@ it run faster:</p>
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on LLVM 2.7, this section lists some "gotchas" that you may run into upgrading
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from the previous release.</p>
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renamed "Release" -> "Release+Asserts"; "Release-Asserts" -> "Release etc.
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RegisterPass<> -> INTIALIZE_PASS()
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<ul>
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<li>.ll file doesn't produce #uses comments anymore, to get them, run a .bc file
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through "llvm-dis --show-annotations".</li>
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<li>MSIL Backend removed.</li>
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<li>ABCD and SSI passes removed.</li>
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<li>'Union' LLVM IR feature removed.</li>
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<li>SCCVN pass removed.</li>
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</ul>
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<p>In addition, many APIs have changed in this release. Some of the major LLVM
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API changes are:</p>
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<ul>
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</ul>
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@ -844,8 +863,8 @@ href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">LLVMdev list</a>.</p>
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<ul>
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<li>The Alpha, SPU, MIPS, PIC16, Blackfin, MSP430, SystemZ and MicroBlaze
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backends are experimental.</li>
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<li><tt>llc</tt> "<tt>-filetype=asm</tt>" (the default) is the only
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supported value for this option. XXX Update me</li>
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<li><tt>llc</tt> "<tt>-filetype=obj</tt>" is experimental on all targets
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other than darwin-i386 and darwin-x86_64.</li>
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</ul>
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</div>
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Loading…
Reference in New Issue