[AArch64] allow v4f16 types when FullFP16 is supported
Support for scalars was committed in r311154, this adds support for allowing v4f16 vector types (thus avoiding conversions from/to single precision for these types). Differential Revision: https://reviews.llvm.org/D37145 llvm-svn: 312104
This commit is contained in:
Sjoerd Meijer
parent
767d98bad8
commit
be5b60f735
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@ -326,17 +326,27 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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else
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setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
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setOperationAction(ISD::FREM, MVT::f16, Promote);
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setOperationAction(ISD::FPOW, MVT::f16, Promote);
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setOperationAction(ISD::FPOWI, MVT::f16, Promote);
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setOperationAction(ISD::FCOS, MVT::f16, Promote);
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setOperationAction(ISD::FSIN, MVT::f16, Promote);
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setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
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setOperationAction(ISD::FEXP, MVT::f16, Promote);
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setOperationAction(ISD::FEXP2, MVT::f16, Promote);
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setOperationAction(ISD::FLOG, MVT::f16, Promote);
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setOperationAction(ISD::FLOG2, MVT::f16, Promote);
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setOperationAction(ISD::FLOG10, MVT::f16, Promote);
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setOperationAction(ISD::FREM, MVT::f16, Promote);
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setOperationAction(ISD::FREM, MVT::v4f16, Promote);
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setOperationAction(ISD::FPOW, MVT::f16, Promote);
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setOperationAction(ISD::FPOW, MVT::v4f16, Promote);
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setOperationAction(ISD::FPOWI, MVT::f16, Promote);
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setOperationAction(ISD::FCOS, MVT::f16, Promote);
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setOperationAction(ISD::FCOS, MVT::v4f16, Promote);
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setOperationAction(ISD::FSIN, MVT::f16, Promote);
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setOperationAction(ISD::FSIN, MVT::v4f16, Promote);
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setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
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setOperationAction(ISD::FSINCOS, MVT::v4f16, Promote);
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setOperationAction(ISD::FEXP, MVT::f16, Promote);
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setOperationAction(ISD::FEXP, MVT::v4f16, Promote);
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setOperationAction(ISD::FEXP2, MVT::f16, Promote);
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setOperationAction(ISD::FEXP2, MVT::v4f16, Promote);
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setOperationAction(ISD::FLOG, MVT::f16, Promote);
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setOperationAction(ISD::FLOG, MVT::v4f16, Promote);
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setOperationAction(ISD::FLOG2, MVT::f16, Promote);
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setOperationAction(ISD::FLOG2, MVT::v4f16, Promote);
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setOperationAction(ISD::FLOG10, MVT::f16, Promote);
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setOperationAction(ISD::FLOG10, MVT::v4f16, Promote);
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if (!Subtarget->hasFullFP16()) {
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setOperationAction(ISD::SELECT, MVT::f16, Promote);
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@ -361,53 +371,39 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
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setOperationAction(ISD::FMINNAN, MVT::f16, Promote);
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setOperationAction(ISD::FMAXNAN, MVT::f16, Promote);
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// promote v4f16 to v4f32 when that is known to be safe.
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setOperationAction(ISD::FADD, MVT::v4f16, Promote);
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setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
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setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
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setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
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setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
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setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
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AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
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AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
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AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
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AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
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AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
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AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
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setOperationAction(ISD::FABS, MVT::v4f16, Expand);
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setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
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setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
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setOperationAction(ISD::FMA, MVT::v4f16, Expand);
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setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
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setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
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setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
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setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
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setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
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setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
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setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
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setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
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setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
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setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
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}
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// v4f16 is also a storage-only type, so promote it to v4f32 when that is
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// known to be safe.
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setOperationAction(ISD::FADD, MVT::v4f16, Promote);
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setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
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setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
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setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
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setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
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setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
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AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
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AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
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AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
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AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
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AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
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AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
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// Expand all other v4f16 operations.
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// FIXME: We could generate better code by promoting some operations to
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// a pair of v4f32s
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setOperationAction(ISD::FABS, MVT::v4f16, Expand);
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setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
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setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
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setOperationAction(ISD::FCOS, MVT::v4f16, Expand);
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setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
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setOperationAction(ISD::FMA, MVT::v4f16, Expand);
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setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
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setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
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setOperationAction(ISD::FPOW, MVT::v4f16, Expand);
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setOperationAction(ISD::FREM, MVT::v4f16, Expand);
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setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
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setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
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setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
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setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
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setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
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setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
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setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
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setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
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setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
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setOperationAction(ISD::FEXP, MVT::v4f16, Expand);
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setOperationAction(ISD::FEXP2, MVT::v4f16, Expand);
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setOperationAction(ISD::FLOG, MVT::v4f16, Expand);
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setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
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setOperationAction(ISD::FLOG10, MVT::v4f16, Expand);
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// v8f16 is also a storage-only type, so expand it.
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setOperationAction(ISD::FABS, MVT::v8f16, Expand);
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setOperationAction(ISD::FADD, MVT::v8f16, Expand);
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@ -1,14 +1,30 @@
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; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
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; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -mattr=-fullfp16 | FileCheck %s
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; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -mattr=+fullfp16 | FileCheck %s --check-prefix=CHECK-FP16
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;;; Float vectors
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%v2f32 = type <2 x float>
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; CHECK: test_v2f32.sqrt:
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%v4f16 = type <4 x half>
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; CHECK-LABEL: test_v2f32.sqrt:
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define %v2f32 @test_v2f32.sqrt(%v2f32 %a) {
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; CHECK: fsqrt.2s
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%1 = call %v2f32 @llvm.sqrt.v2f32(%v2f32 %a)
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ret %v2f32 %1
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}
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define %v4f16 @test_v4f16.sqrt(%v4f16 %a) {
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; CHECK-LABEL: test_v4f16.sqrt:
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; CHECK: fsqrt s{{.}}, s{{.}}
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; CHECK: fsqrt s{{.}}, s{{.}}
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; CHECK: fsqrt s{{.}}, s{{.}}
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; CHECK: fsqrt s{{.}}, s{{.}}
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; CHECK-FP16-LABEL: test_v4f16.sqrt:
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; CHECK-FP16: fsqrt.4h
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; CHECK-FP16-NEXT: ret
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%1 = call %v4f16 @llvm.sqrt.v4f16(%v4f16 %a)
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ret %v4f16 %1
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}
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; CHECK: test_v2f32.powi:
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define %v2f32 @test_v2f32.powi(%v2f32 %a, i32 %b) {
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; CHECK: pow
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@ -63,50 +79,142 @@ define %v2f32 @test_v2f32.log2(%v2f32 %a) {
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%1 = call %v2f32 @llvm.log2.v2f32(%v2f32 %a)
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ret %v2f32 %1
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}
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; CHECK: test_v2f32.fma:
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; CHECK-LABEL: test_v2f32.fma:
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define %v2f32 @test_v2f32.fma(%v2f32 %a, %v2f32 %b, %v2f32 %c) {
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; CHECK: fma
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; CHECK: fmla.2s
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%1 = call %v2f32 @llvm.fma.v2f32(%v2f32 %a, %v2f32 %b, %v2f32 %c)
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ret %v2f32 %1
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}
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; CHECK: test_v2f32.fabs:
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define %v4f16 @test_v4f16.fma(%v4f16 %a, %v4f16 %b, %v4f16 %c) {
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; CHECK-LABEL: test_v4f16.fma:
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; CHECK: fmadd s{{.}}, s{{.}}, s{{.}}, s{{.}}
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; CHECK: fmadd s{{.}}, s{{.}}, s{{.}}, s{{.}}
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; CHECK: fmadd s{{.}}, s{{.}}, s{{.}}, s{{.}}
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; CHECK: fmadd s{{.}}, s{{.}}, s{{.}}, s{{.}}
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; CHECK-FP16-LABEL: test_v4f16.fma:
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; CHECK-FP16: fmla.4h
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%1 = call %v4f16 @llvm.fma.v4f16(%v4f16 %a, %v4f16 %b, %v4f16 %c)
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ret %v4f16 %1
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}
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; CHECK-LABEL: test_v2f32.fabs:
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define %v2f32 @test_v2f32.fabs(%v2f32 %a) {
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; CHECK: fabs
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; CHECK: fabs.2s
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%1 = call %v2f32 @llvm.fabs.v2f32(%v2f32 %a)
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ret %v2f32 %1
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}
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; CHECK: test_v2f32.floor:
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define %v4f16 @test_v4f16.fabs(%v4f16 %a) {
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; CHECK-LABEL: test_v4f16.fabs:
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; CHECK: fabs s{{.}}, s{{.}}
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; CHECK: fabs s{{.}}, s{{.}}
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; CHECK: fabs s{{.}}, s{{.}}
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; CHECK: fabs s{{.}}, s{{.}}
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; CHECK-FP16-LABEL: test_v4f16.fabs:
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; CHECK-FP16: fabs.4h
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; CHECK-FP16-NEXT: ret
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%1 = call %v4f16 @llvm.fabs.v4f16(%v4f16 %a)
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ret %v4f16 %1
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}
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; CHECK-LABEL: test_v2f32.floor:
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define %v2f32 @test_v2f32.floor(%v2f32 %a) {
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; CHECK: frintm.2s
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%1 = call %v2f32 @llvm.floor.v2f32(%v2f32 %a)
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ret %v2f32 %1
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}
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; CHECK: test_v2f32.ceil:
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define %v4f16 @test_v4f16.floor(%v4f16 %a) {
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; CHECK-LABEL: test_v4f16.floor:
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; CHECK: frintm s{{.}}, s{{.}}
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; CHECK: frintm s{{.}}, s{{.}}
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; CHECK: frintm s{{.}}, s{{.}}
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; CHECK: frintm s{{.}}, s{{.}}
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; CHECK-FP16-LABEL: test_v4f16.floor:
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; CHECK-FP16: frintm.4h
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; CHECK-FP16-NEXT: ret
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%1 = call %v4f16 @llvm.floor.v4f16(%v4f16 %a)
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ret %v4f16 %1
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}
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; CHECK-LABEL: test_v2f32.ceil:
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define %v2f32 @test_v2f32.ceil(%v2f32 %a) {
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; CHECK: frintp.2s
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%1 = call %v2f32 @llvm.ceil.v2f32(%v2f32 %a)
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ret %v2f32 %1
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}
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; CHECK: test_v2f32.trunc:
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define %v4f16 @test_v4f16.ceil(%v4f16 %a) {
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; CHECK-LABEL: test_v4f16.ceil:
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; CHECK: frintp s{{.}}, s{{.}}
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; CHECK: frintp s{{.}}, s{{.}}
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; CHECK: frintp s{{.}}, s{{.}}
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; CHECK: frintp s{{.}}, s{{.}}
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; CHECK-FP16-LABEL: test_v4f16.ceil:
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; CHECK-FP16: frintp.4h
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; CHECK-FP16-NEXT: ret
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%1 = call %v4f16 @llvm.ceil.v4f16(%v4f16 %a)
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ret %v4f16 %1
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}
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; CHECK-LABEL: test_v2f32.trunc:
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define %v2f32 @test_v2f32.trunc(%v2f32 %a) {
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; CHECK: frintz.2s
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%1 = call %v2f32 @llvm.trunc.v2f32(%v2f32 %a)
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ret %v2f32 %1
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}
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; CHECK: test_v2f32.rint:
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define %v4f16 @test_v4f16.trunc(%v4f16 %a) {
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; CHECK-LABEL: test_v4f16.trunc:
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; CHECK: frintz s{{.}}, s{{.}}
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; CHECK: frintz s{{.}}, s{{.}}
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; CHECK: frintz s{{.}}, s{{.}}
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; CHECK: frintz s{{.}}, s{{.}}
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; CHECK-FP16-LABEL: test_v4f16.trunc:
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; CHECK-FP16: frintz.4h
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; CHECK-FP16-NEXT: ret
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%1 = call %v4f16 @llvm.trunc.v4f16(%v4f16 %a)
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ret %v4f16 %1
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}
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; CHECK-LABEL: test_v2f32.rint:
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define %v2f32 @test_v2f32.rint(%v2f32 %a) {
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; CHECK: frintx.2s
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%1 = call %v2f32 @llvm.rint.v2f32(%v2f32 %a)
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ret %v2f32 %1
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}
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; CHECK: test_v2f32.nearbyint:
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define %v4f16 @test_v4f16.rint(%v4f16 %a) {
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; CHECK-LABEL: test_v4f16.rint:
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; CHECK: frintx s{{.}}, s{{.}}
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; CHECK: frintx s{{.}}, s{{.}}
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; CHECK: frintx s{{.}}, s{{.}}
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; CHECK: frintx s{{.}}, s{{.}}
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; CHECK-FP16-LABEL: test_v4f16.rint:
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; CHECK-FP16: frintx.4h
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; CHECK-FP16-NEXT: ret
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%1 = call %v4f16 @llvm.rint.v4f16(%v4f16 %a)
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ret %v4f16 %1
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}
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; CHECK-LABEL: test_v2f32.nearbyint:
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define %v2f32 @test_v2f32.nearbyint(%v2f32 %a) {
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; CHECK: frinti.2s
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%1 = call %v2f32 @llvm.nearbyint.v2f32(%v2f32 %a)
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ret %v2f32 %1
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}
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define %v4f16 @test_v4f16.nearbyint(%v4f16 %a) {
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; CHECK-LABEL: test_v4f16.nearbyint:
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; CHECK: frinti s{{.}}, s{{.}}
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; CHECK: frinti s{{.}}, s{{.}}
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; CHECK: frinti s{{.}}, s{{.}}
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; CHECK: frinti s{{.}}, s{{.}}
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; CHECK-FP16-LABEL: test_v4f16.nearbyint:
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; CHECK-FP16: frinti.4h
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; CHECK-FP16-NEXT: ret
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%1 = call %v4f16 @llvm.nearbyint.v4f16(%v4f16 %a)
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ret %v4f16 %1
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}
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declare %v2f32 @llvm.sqrt.v2f32(%v2f32) #0
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declare %v4f16 @llvm.sqrt.v4f16(%v4f16) #0
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declare %v2f32 @llvm.powi.v2f32(%v2f32, i32) #0
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declare %v2f32 @llvm.sin.v2f32(%v2f32) #0
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declare %v2f32 @llvm.cos.v2f32(%v2f32) #0
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@ -116,13 +224,27 @@ declare %v2f32 @llvm.exp2.v2f32(%v2f32) #0
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declare %v2f32 @llvm.log.v2f32(%v2f32) #0
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declare %v2f32 @llvm.log10.v2f32(%v2f32) #0
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declare %v2f32 @llvm.log2.v2f32(%v2f32) #0
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declare %v2f32 @llvm.fma.v2f32(%v2f32, %v2f32, %v2f32) #0
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declare %v4f16 @llvm.fma.v4f16(%v4f16, %v4f16, %v4f16) #0
|
||||
|
||||
declare %v2f32 @llvm.fabs.v2f32(%v2f32) #0
|
||||
declare %v4f16 @llvm.fabs.v4f16(%v4f16) #0
|
||||
|
||||
declare %v2f32 @llvm.floor.v2f32(%v2f32) #0
|
||||
declare %v4f16 @llvm.floor.v4f16(%v4f16) #0
|
||||
|
||||
declare %v2f32 @llvm.ceil.v2f32(%v2f32) #0
|
||||
declare %v4f16 @llvm.ceil.v4f16(%v4f16) #0
|
||||
|
||||
declare %v2f32 @llvm.trunc.v2f32(%v2f32) #0
|
||||
declare %v4f16 @llvm.trunc.v4f16(%v4f16) #0
|
||||
|
||||
declare %v2f32 @llvm.rint.v2f32(%v2f32) #0
|
||||
declare %v4f16 @llvm.rint.v4f16(%v4f16) #0
|
||||
|
||||
declare %v2f32 @llvm.nearbyint.v2f32(%v2f32) #0
|
||||
declare %v4f16 @llvm.nearbyint.v4f16(%v4f16) #0
|
||||
|
||||
;;;
|
||||
|
||||
|
|
|
|||
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