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Change latencies for Load, Store and Branch instructions. 

llvm-svn: 1965
This commit is contained in:
Vikram S. Adve 2002-03-24 03:33:53 +00:00
parent 72213c9a66
commit be08b5ea15
1 changed files with 42 additions and 40 deletions
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54
llvm/lib/Target/Sparc/SparcInstr.def
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@ -159,13 +159,13 @@ I(FITOQ, "fitoq", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLA
// Branch on integer comparison with zero.
// Annul bit specifies if intruction in delay slot is annulled(1) or not(0).
// PredictTaken bit hints if branch should be predicted taken(1) or not(0).
// Latency includes the delay slot.
I(BRZ , "brz", 2, -1, B15, true , 1, 2, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG)
I(BRLEZ, "brlez", 2, -1, B15, true , 1, 2, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG)
I(BRLZ , "brlz", 2, -1, B15, true , 1, 2, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG)
I(BRNZ , "brnz", 2, -1, B15, true , 1, 2, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG)
I(BRGZ , "brgz", 2, -1, B15, true , 1, 2, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG)
I(BRGEZ, "brgez", 2, -1, B15, true , 1, 2, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG)
// Latency excludes the delay slot since it can be issued in same cycle.
I(BRZ , "brz", 2, -1, B15, true , 1, 1, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG)
I(BRLEZ, "brlez", 2, -1, B15, true , 1, 1, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG)
I(BRLZ , "brlz", 2, -1, B15, true , 1, 1, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG)
I(BRNZ , "brnz", 2, -1, B15, true , 1, 1, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG)
I(BRGZ , "brgz", 2, -1, B15, true , 1, 1, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG)
I(BRGEZ, "brgez", 2, -1, B15, true , 1, 1, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG)
// Branch on integer condition code.
// The first argument specifies the ICC register: %icc or %xcc
@ -389,36 +389,38 @@ I(FMOVQFULE, "fmovqule",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_F
I(FMOVQFO , "fmovqo", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG)
// Load integer instructions
// Latency includes 1 cycle for address generation (Sparc IIi)
// Latency includes 1 cycle for address generation (Sparc IIi),
// plus 3 cycles assumed for average miss penalty (bias towards L1 hits).
// Signed loads of less than 64 bits need an extra cycle for sign-extension.
//
// Not reflected here: After a 3-cycle loads, all subsequent consecutive
// loads also require 3 cycles to avoid contention for the load return
// stage. Latency returns to 2 cycles after the first cycle with no load.
I(LDSB, "ldsb", 3, 2, B12, true , 0, 3, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
I(LDSH, "ldsh", 3, 2, B12, true , 0, 3, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
I(LDSW, "ldsw", 3, 2, B12, true , 0, 3, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
I(LDUB, "ldub", 3, 2, B12, true , 0, 2, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
I(LDUH, "lduh", 3, 2, B12, true , 0, 2, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
I(LDUW, "lduw", 3, 2, B12, true , 0, 2, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
I(LDX , "ldx", 3, 2, B12, true , 0, 2, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
I(LDSB, "ldsb", 3, 2, B12, true , 0, 6, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
I(LDSH, "ldsh", 3, 2, B12, true , 0, 6, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
I(LDSW, "ldsw", 3, 2, B12, true , 0, 6, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
I(LDUB, "ldub", 3, 2, B12, true , 0, 5, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
I(LDUH, "lduh", 3, 2, B12, true , 0, 5, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
I(LDUW, "lduw", 3, 2, B12, true , 0, 5, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
I(LDX , "ldx", 3, 2, B12, true , 0, 5, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG)
// Load floating-point instructions
// Latency includes 1 cycle for address generation (Sparc IIi)
I(LD , "ld", 3, 2, B12, true , 0, 2, SPARC_LD, M_FLOAT_FLAG | M_LOAD_FLAG)
I(LDD, "ldd", 3, 2, B12, true , 0, 2, SPARC_LD, M_FLOAT_FLAG | M_LOAD_FLAG)
I(LDQ, "ldq", 3, 2, B12, true , 0, 2, SPARC_LD, M_FLOAT_FLAG | M_LOAD_FLAG)
I(LD , "ld", 3, 2, B12, true , 0, 5, SPARC_LD, M_FLOAT_FLAG | M_LOAD_FLAG)
I(LDD, "ldd", 3, 2, B12, true , 0, 5, SPARC_LD, M_FLOAT_FLAG | M_LOAD_FLAG)
I(LDQ, "ldq", 3, 2, B12, true , 0, 5, SPARC_LD, M_FLOAT_FLAG | M_LOAD_FLAG)
// Store integer instructions
// Latency includes 1 cycle for address generation (Sparc IIi)
I(STB, "stb", 3, -1, B12, true , 0, 2, SPARC_ST, M_INT_FLAG | M_STORE_FLAG)
I(STH, "sth", 3, -1, B12, true , 0, 2, SPARC_ST, M_INT_FLAG | M_STORE_FLAG)
I(STW, "stw", 3, -1, B12, true , 0, 2, SPARC_ST, M_INT_FLAG | M_STORE_FLAG)
I(STX, "stx", 3, -1, B12, true , 0, 3, SPARC_ST, M_INT_FLAG | M_STORE_FLAG)
// Store integer instructions.
// Requires 1 cycle for address generation (Sparc IIi).
// Default latency is 0 because value is not explicitly used.
I(STB, "stb", 3, -1, B12, true , 0, 0, SPARC_ST, M_INT_FLAG | M_STORE_FLAG)
I(STH, "sth", 3, -1, B12, true , 0, 0, SPARC_ST, M_INT_FLAG | M_STORE_FLAG)
I(STW, "stw", 3, -1, B12, true , 0, 0, SPARC_ST, M_INT_FLAG | M_STORE_FLAG)
I(STX, "stx", 3, -1, B12, true , 0, 0, SPARC_ST, M_INT_FLAG | M_STORE_FLAG)
// Store floating-point instructions (Sparc IIi)
I(ST , "st", 3, -1, B12, true , 0, 2, SPARC_ST, M_FLOAT_FLAG | M_STORE_FLAG)
I(STD, "std", 3, -1, B12, true , 0, 2, SPARC_ST, M_FLOAT_FLAG | M_STORE_FLAG)
I(ST , "st", 3, -1, B12, true , 0, 0, SPARC_ST, M_FLOAT_FLAG | M_STORE_FLAG)
I(STD, "std", 3, -1, B12, true , 0, 0, SPARC_ST, M_FLOAT_FLAG | M_STORE_FLAG)
// Call, Return and "Jump and link".
// Latency includes the delay slot.