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[PowerPC] Change Test Options [NFC] 

Patch by amyk

llvm-svn: 340639
This commit is contained in:
Stefan Pintilie 2018-08-24 19:24:20 +00:00
parent 1c0fde61a6
commit bddd7d8b7b
3 changed files with 782 additions and 750 deletions
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852
llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
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72
llvm/test/CodeGen/PowerPC/vsx-spill.ll
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@ -1,13 +1,17 @@
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx < %s | FileCheck \
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
; RUN: -check-prefix=CHECK-REG %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | \
; RUN: FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | \
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | \
; RUN: FileCheck -check-prefix=CHECK-FISL %s
; RUN: llc -verify-machineinstrs -mcpu=pwr9 < %s | FileCheck \
; RUN: -check-prefix=CHECK-P9-REG %s
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -fast-isel -O0 < %s | FileCheck \
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \
; RUN: -ppc-asm-full-reg-names < %s | FileCheck -check-prefix=CHECK-P9-REG %s
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -fast-isel -O0 \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
; RUN: -check-prefix=CHECK-P9-FISL %s
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
@ -18,26 +22,26 @@ entry:
br label %return
; CHECK-REG: @foo1
; CHECK-REG: xxlor [[R1:[0-9]+]], 1, 1
; CHECK-REG: xxlor 1, [[R1]], [[R1]]
; CHECK-REG: xxlor v2, f1, f1
; CHECK-REG: xxlor f1, v2, v2
; CHECK-REG: blr
; CHECK-FISL: @foo1
; CHECK-FISL-NOT: lis
; CHECK-FISL-NOT: ori
; CHECK-FISL: li 3, -152
; CHECK-FISL: li r3, -152
; CHECK-FISL-NOT: lis
; CHECK-FISL-NOT: ori
; CHECK-FISL: stxsdx 1, 1, 3
; CHECK-FISL: stxsdx f1, r1, r3
; CHECK-FISL: blr
; CHECK-P9-REG: @foo1
; CHECK-P9-REG: xxlor [[R1:[0-9]+]], 1, 1
; CHECK-P9-REG: xxlor 1, [[R1]], [[R1]]
; CHECK-P9-REG: xxlor v2, f1, f1
; CHECK-P9-REG: xxlor f1, v2, v2
; CHECK-P9-REG: blr
; CHECK-P9-FISL: @foo1
; CHECK-P9-FISL: stfd 31, -8(1)
; CHECK-P9-FISL: stfd f31, -8(r1)
; CHECK-P9-FISL: blr
return: ; preds = %entry
@ -51,25 +55,25 @@ entry:
br label %return
; CHECK-REG: @foo2
; CHECK-REG: {{xxlor|xsadddp}} [[R1:[0-9]+]], 1, 1
; CHECK-REG: {{xxlor|xsadddp}} 1, [[R1]], [[R1]]
; CHECK-REG: {{xxlor|xsadddp}} v2, f1, f1
; CHECK-REG: {{xxlor|xsadddp}} f1, f0, f0
; CHECK-REG: blr
; CHECK-FISL: @foo2
; CHECK-FISL: xsadddp [[R1:[0-9]+]], 1, 1
; CHECK-FISL: stxsdx [[R1]], [[R1]], 3
; CHECK-FISL: lxsdx [[R1]], [[R1]], 3
; CHECK-FISL: xsadddp f1, f1, f1
; CHECK-FISL: stxsdx f1, r1, r3
; CHECK-FISL: lxsdx f1, r1, r3
; CHECK-FISL: blr
; CHECK-P9-REG: @foo2
; CHECK-P9-REG: {{xxlor|xsadddp}} [[R1:[0-9]+]], 1, 1
; CHECK-P9-REG: {{xxlor|xsadddp}} 1, [[R1]], [[R1]]
; CHECK-P9-REG: {{xxlor|xsadddp}} v2, f1, f1
; CHECK-P9-REG: {{xxlor|xsadddp}} f1, v2, v2
; CHECK-P9-REG: blr
; CHECK-P9-FISL: @foo2
; CHECK-P9-FISL: xsadddp [[R1:[0-9]+]], 1, 1
; CHECK-P9-FISL: stfd [[R1]], [[OFF:[0-9\-]+]](1)
; CHECK-P9-FISL: lfd [[R1]], [[OFF]](1)
; CHECK-P9-FISL: xsadddp f1, f1, f1
; CHECK-P9-FISL: stfd f1, -152(r1)
; CHECK-P9-FISL: lfd f1, -152(r1)
; CHECK-P9-FISL: blr
return: ; preds = %entry
@ -82,20 +86,20 @@ entry:
br label %return
; CHECK: @foo3
; CHECK: stxsdx 1,
; CHECK: lxsdx [[R1:[0-9]+]],
; CHECK: xsadddp 1, [[R1]], [[R1]]
; CHECK: stxsdx f1, r1, r3
; CHECK: lxsdx f0, r1, r3
; CHECK: xsadddp f1, f0, f0
; CHECK: blr
; CHECK-P9-REG-LABEL: foo3
; CHECK-P9-REG: stfd 1, [[OFF:[0-9\-]+]](1)
; CHECK-P9-REG: lfd [[FPR:[0-9]+]], [[OFF]](1)
; CHECK-P9-REG: xsadddp 1, [[FPR]], [[FPR]]
; CHECK-P9-REG: stdu r1, -400(r1)
; CHECK-P9-REG: lfd f30, 384(r1)
; CHECK-P9-REG: xsadddp f1, f0, f0
; CHECK-P9-FISL-LABEL: foo3
; CHECK-P9-FISL: stfd 1, [[OFF:[0-9\-]+]](1)
; CHECK-P9-FISL: lfd [[FPR:[0-9]+]], [[OFF]](1)
; CHECK-P9-FISL: xsadddp 1, [[FPR]], [[FPR]]
; CHECK-P9-FISL: stdu r1, -400(r1)
; CHECK-P9-FISL: lfd f0, 56(r1)
; CHECK-P9-FISL: xsadddp f1, f0, f0
return: ; preds = %entry
%b = fadd double %a, %a
ret double %b

608
llvm/test/CodeGen/PowerPC/vsx.ll
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