AMDGPU: Make AllocationPriority of SGPRs higher than VGPRs
Since SGPRs should spill to VGPRs, they should be allocated first. I don't think this is sufficient for SGPRs to always spill to VGPRs though. llvm-svn: 289671
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@ -130,7 +130,9 @@ def M0_CLASS : RegisterClass<"AMDGPU", [i32], 32, (add M0)> {
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// SGPR 32-bit registers
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def SGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16], 32,
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(add (sequence "SGPR%u", 0, 103))> {
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let AllocationPriority = 1;
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// Give all SGPR classes higher priority than VGPR classes, because
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// we want to spill SGPRs to VGPRs.
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let AllocationPriority = 7;
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}
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// SGPR 64-bit registers
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@ -259,23 +261,23 @@ def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
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def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16], 32,
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(add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI,
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TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI)> {
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let AllocationPriority = 1;
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let AllocationPriority = 7;
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}
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def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32, i16, f16], 32,
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(add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI)> {
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let AllocationPriority = 1;
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let AllocationPriority = 7;
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}
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// Register class for all scalar registers (SGPRs + Special Registers)
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def SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16], 32,
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(add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI)> {
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let AllocationPriority = 1;
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let AllocationPriority = 7;
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}
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def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add SGPR_64Regs)> {
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let CopyCost = 1;
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let AllocationPriority = 2;
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let AllocationPriority = 8;
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}
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def TTMP_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add TTMP_64Regs)> {
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@ -285,20 +287,20 @@ def TTMP_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add TTMP_64Regs)>
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def SReg_64_XEXEC : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
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(add SGPR_64, VCC, FLAT_SCR, TTMP_64, TBA, TMA)> {
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let CopyCost = 1;
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let AllocationPriority = 2;
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let AllocationPriority = 8;
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}
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def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
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(add SReg_64_XEXEC, EXEC)> {
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let CopyCost = 1;
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let AllocationPriority = 2;
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let AllocationPriority = 8;
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}
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// Requires 2 s_mov_b64 to copy
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let CopyCost = 2 in {
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def SGPR_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add SGPR_128Regs)> {
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let AllocationPriority = 4;
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let AllocationPriority = 10;
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}
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def TTMP_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add TTMP_128Regs)> {
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@ -306,7 +308,7 @@ def TTMP_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add TTMP_128R
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}
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def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add SGPR_128, TTMP_128)> {
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let AllocationPriority = 4;
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let AllocationPriority = 10;
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}
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} // End CopyCost = 2
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@ -314,13 +316,13 @@ def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add SGPR_128,
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def SReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add SGPR_256)> {
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// Requires 4 s_mov_b64 to copy
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let CopyCost = 4;
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let AllocationPriority = 5;
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let AllocationPriority = 11;
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}
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def SReg_512 : RegisterClass<"AMDGPU", [v64i8, v16i32], 32, (add SGPR_512)> {
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// Requires 8 s_mov_b64 to copy
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let CopyCost = 8;
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let AllocationPriority = 6;
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let AllocationPriority = 12;
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}
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// Register class for all vector registers (VGPRs + Interploation Registers)
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