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AMDGPU: Make sure to reserve super registers 

I think this could potentially have broken if
one of the super registers were allocated
that contain v254/v255.

llvm-svn: 246051
This commit is contained in:
Matt Arsenault 2015-08-26 18:54:50 +00:00
parent 8b3dda3f71
commit bd66061db7
2 changed files with 18 additions and 16 deletions
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31
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
View File

@ -26,23 +26,25 @@ using namespace llvm;
SIRegisterInfo::SIRegisterInfo() : AMDGPURegisterInfo() {}
void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
MCRegAliasIterator R(Reg, this, true);
for (; R.isValid(); ++R)
Reserved.set(*R);
}
BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
Reserved.set(AMDGPU::EXEC);
// EXEC_LO and EXEC_HI could be allocated and used as regular register,
// but this seems likely to result in bugs, so I'm marking them as reserved.
Reserved.set(AMDGPU::EXEC_LO);
Reserved.set(AMDGPU::EXEC_HI);
Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
Reserved.set(AMDGPU::FLAT_SCR);
Reserved.set(AMDGPU::FLAT_SCR_LO);
Reserved.set(AMDGPU::FLAT_SCR_HI);
// EXEC_LO and EXEC_HI could be allocated and used as regular register, but
// this seems likely to result in bugs, so I'm marking them as reserved.
reserveRegisterTuples(Reserved, AMDGPU::EXEC);
reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR);
// Reserve some VGPRs to use as temp registers in case we have to spill VGPRs
Reserved.set(AMDGPU::VGPR255);
Reserved.set(AMDGPU::VGPR254);
reserveRegisterTuples(Reserved, AMDGPU::VGPR254);
reserveRegisterTuples(Reserved, AMDGPU::VGPR255);
// Tonga and Iceland can only allocate a fixed number of SGPRs due
// to a hw bug.
@ -54,10 +56,7 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
for (unsigned i = Limit; i < NumSGPRs; ++i) {
unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i);
MCRegAliasIterator R = MCRegAliasIterator(Reg, this, true);
for (; R.isValid(); ++R)
Reserved.set(*R);
reserveRegisterTuples(Reserved, Reg);
}
}

3
llvm/lib/Target/AMDGPU/SIRegisterInfo.h
View File

@ -23,7 +23,10 @@
namespace llvm {
struct SIRegisterInfo : public AMDGPURegisterInfo {
private:
void reserveRegisterTuples(BitVector &, unsigned Reg) const;
public:
SIRegisterInfo();
BitVector getReservedRegs(const MachineFunction &MF) const override;