AMDGPU: Rename spill operands to match real instruction
llvm-svn: 281823
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d99ef1144b
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@ -1210,8 +1210,8 @@ multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> {
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SchedRW = [WriteVMEM] in {
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SchedRW = [WriteVMEM] in {
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def _SAVE : VPseudoInstSI <
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def _SAVE : VPseudoInstSI <
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(outs),
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(outs),
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(ins vgpr_class:$vdata, i32imm:$vaddr, SReg_128:$scratch_rsrc,
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(ins vgpr_class:$vdata, i32imm:$vaddr, SReg_128:$srsrc,
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SReg_32:$scratch_offset, i32imm:$offset)> {
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SReg_32:$soffset, i32imm:$offset)> {
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let mayStore = 1;
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let mayStore = 1;
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let mayLoad = 0;
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let mayLoad = 0;
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// (2 * 4) + (8 * num_subregs) bytes maximum
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// (2 * 4) + (8 * num_subregs) bytes maximum
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@ -1220,7 +1220,7 @@ multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> {
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def _RESTORE : VPseudoInstSI <
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def _RESTORE : VPseudoInstSI <
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(outs vgpr_class:$vdata),
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(outs vgpr_class:$vdata),
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(ins i32imm:$vaddr, SReg_128:$scratch_rsrc, SReg_32:$scratch_offset,
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(ins i32imm:$vaddr, SReg_128:$srsrc, SReg_32:$soffset,
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i32imm:$offset)> {
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i32imm:$offset)> {
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let mayStore = 0;
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let mayStore = 0;
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let mayLoad = 1;
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let mayLoad = 1;
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@ -488,9 +488,9 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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Size, Align);
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Size, Align);
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BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_SAVE))
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BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_SAVE))
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.addReg(TmpReg, RegState::Kill) // src
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.addReg(TmpReg, RegState::Kill) // src
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.addFrameIndex(Index) // frame_idx
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.addFrameIndex(Index) // vaddr
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.addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
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.addReg(MFI->getScratchRSrcReg()) // srrsrc
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.addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset
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.addReg(MFI->getScratchWaveOffsetReg()) // soffset
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.addImm(i * 4) // offset
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.addImm(i * 4) // offset
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.addMemOperand(MMO);
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.addMemOperand(MMO);
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}
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}
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@ -546,9 +546,9 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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PtrInfo, MachineMemOperand::MOLoad, Size, Align);
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PtrInfo, MachineMemOperand::MOLoad, Size, Align);
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BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_RESTORE), TmpReg)
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BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_RESTORE), TmpReg)
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.addFrameIndex(Index) // frame_idx
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.addFrameIndex(Index) // vaddr
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.addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
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.addReg(MFI->getScratchRSrcReg()) // srsrc
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.addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset
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.addReg(MFI->getScratchWaveOffsetReg()) // soffset
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.addImm(i * 4) // offset
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.addImm(i * 4) // offset
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.addMemOperand(MMO);
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.addMemOperand(MMO);
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BuildMI(*MBB, MI, DL,
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BuildMI(*MBB, MI, DL,
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@ -576,8 +576,8 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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case AMDGPU::SI_SPILL_V32_SAVE:
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case AMDGPU::SI_SPILL_V32_SAVE:
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buildScratchLoadStore(MI, AMDGPU::BUFFER_STORE_DWORD_OFFSET,
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buildScratchLoadStore(MI, AMDGPU::BUFFER_STORE_DWORD_OFFSET,
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TII->getNamedOperand(*MI, AMDGPU::OpName::vdata),
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TII->getNamedOperand(*MI, AMDGPU::OpName::vdata),
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TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(),
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TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)->getReg(),
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TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(),
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TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg(),
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FrameInfo.getObjectOffset(Index) +
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FrameInfo.getObjectOffset(Index) +
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TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), RS);
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TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), RS);
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MI->eraseFromParent();
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MI->eraseFromParent();
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@ -591,8 +591,8 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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case AMDGPU::SI_SPILL_V512_RESTORE: {
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case AMDGPU::SI_SPILL_V512_RESTORE: {
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buildScratchLoadStore(MI, AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
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buildScratchLoadStore(MI, AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
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TII->getNamedOperand(*MI, AMDGPU::OpName::vdata),
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TII->getNamedOperand(*MI, AMDGPU::OpName::vdata),
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TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(),
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TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)->getReg(),
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TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(),
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TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg(),
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FrameInfo.getObjectOffset(Index) +
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FrameInfo.getObjectOffset(Index) +
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TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), RS);
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TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), RS);
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MI->eraseFromParent();
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MI->eraseFromParent();
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