[Hexagon] Boost profit for word-mask immediates, reduce for others
This avoids unnecessary splitting due to uninteresting immediates. llvm-svn: 328364
This commit is contained in:
Krzysztof Parzyszek
parent
f228276262
commit
bcf0a96f9e
|
|
@ -55,6 +55,8 @@ static cl::opt<int> MaxHSDR("max-hsdr", cl::Hidden, cl::init(-1),
|
|||
cl::desc("Maximum number of split partitions"));
|
||||
static cl::opt<bool> MemRefsFixed("hsdr-no-mem", cl::Hidden, cl::init(true),
|
||||
cl::desc("Do not split loads or stores"));
|
||||
static cl::opt<bool> SplitAll("hsdr-split-all", cl::Hidden, cl::init(false),
|
||||
cl::desc("Split all partitions"));
|
||||
|
||||
namespace {
|
||||
|
||||
|
|
@ -97,6 +99,7 @@ namespace {
|
|||
bool isFixedInstr(const MachineInstr *MI) const;
|
||||
void partitionRegisters(UUSetMap &P2Rs);
|
||||
int32_t profit(const MachineInstr *MI) const;
|
||||
int32_t profit(unsigned Reg) const;
|
||||
bool isProfitable(const USet &Part, LoopRegMap &IRM) const;
|
||||
|
||||
void collectIndRegsForLoop(const MachineLoop *L, USet &Rs);
|
||||
|
|
@ -306,13 +309,10 @@ void HexagonSplitDoubleRegs::partitionRegisters(UUSetMap &P2Rs) {
|
|||
|
||||
static inline int32_t profitImm(unsigned Lo, unsigned Hi) {
|
||||
int32_t P = 0;
|
||||
bool LoZ1 = false, HiZ1 = false;
|
||||
if (Lo == 0 || Lo == 0xFFFFFFFF)
|
||||
P += 10, LoZ1 = true;
|
||||
P += 10;
|
||||
if (Hi == 0 || Hi == 0xFFFFFFFF)
|
||||
P += 10, HiZ1 = true;
|
||||
if (!LoZ1 && !HiZ1 && Lo == Hi)
|
||||
P += 3;
|
||||
P += 10;
|
||||
return P;
|
||||
}
|
||||
|
||||
|
|
@ -368,8 +368,11 @@ int32_t HexagonSplitDoubleRegs::profit(const MachineInstr *MI) const {
|
|||
|
||||
case Hexagon::A2_andp:
|
||||
case Hexagon::A2_orp:
|
||||
case Hexagon::A2_xorp:
|
||||
return 1;
|
||||
case Hexagon::A2_xorp: {
|
||||
unsigned Rs = MI->getOperand(1).getReg();
|
||||
unsigned Rt = MI->getOperand(2).getReg();
|
||||
return profit(Rs) + profit(Rt);
|
||||
}
|
||||
|
||||
case Hexagon::S2_asl_i_p_or: {
|
||||
unsigned S = MI->getOperand(3).getImm();
|
||||
|
|
@ -393,6 +396,25 @@ int32_t HexagonSplitDoubleRegs::profit(const MachineInstr *MI) const {
|
|||
return 0;
|
||||
}
|
||||
|
||||
int32_t HexagonSplitDoubleRegs::profit(unsigned Reg) const {
|
||||
assert(TargetRegisterInfo::isVirtualRegister(Reg));
|
||||
|
||||
const MachineInstr *DefI = MRI->getVRegDef(Reg);
|
||||
switch (DefI->getOpcode()) {
|
||||
case Hexagon::A2_tfrpi:
|
||||
case Hexagon::CONST64:
|
||||
case Hexagon::A2_combineii:
|
||||
case Hexagon::A4_combineii:
|
||||
case Hexagon::A4_combineri:
|
||||
case Hexagon::A4_combineir:
|
||||
case Hexagon::A2_combinew:
|
||||
return profit(DefI);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool HexagonSplitDoubleRegs::isProfitable(const USet &Part, LoopRegMap &IRM)
|
||||
const {
|
||||
unsigned FixedNum = 0, LoopPhiNum = 0;
|
||||
|
|
@ -443,6 +465,8 @@ bool HexagonSplitDoubleRegs::isProfitable(const USet &Part, LoopRegMap &IRM)
|
|||
TotalP -= 20*LoopPhiNum;
|
||||
|
||||
DEBUG(dbgs() << "Partition profit: " << TotalP << '\n');
|
||||
if (SplitAll)
|
||||
return true;
|
||||
return TotalP > 0;
|
||||
}
|
||||
|
||||
|
|
@ -1160,12 +1184,12 @@ bool HexagonSplitDoubleRegs::splitPartition(const USet &Part) {
|
|||
}
|
||||
|
||||
bool HexagonSplitDoubleRegs::runOnMachineFunction(MachineFunction &MF) {
|
||||
DEBUG(dbgs() << "Splitting double registers in function: "
|
||||
<< MF.getName() << '\n');
|
||||
|
||||
if (skipFunction(MF.getFunction()))
|
||||
return false;
|
||||
|
||||
DEBUG(dbgs() << "Splitting double registers in function: "
|
||||
<< MF.getName() << '\n');
|
||||
|
||||
auto &ST = MF.getSubtarget<HexagonSubtarget>();
|
||||
TRI = ST.getRegisterInfo();
|
||||
TII = ST.getInstrInfo();
|
||||
|
|
|
|||
|
|
@ -0,0 +1,42 @@
|
|||
; RUN: llc -march=hexagon < %s | FileCheck %s
|
||||
;
|
||||
; Make sure that the A2_andp is not split.
|
||||
;
|
||||
; CHECK: loop0([[LOOP:.LBB[_0-9]+]],{{.*}})
|
||||
; CHECK: [[LOOP]]:
|
||||
; CHECK: and(r{{[0-9]+}}:{{[0-9]+}},r{{[0-9]+}}:{{[0-9]+}})
|
||||
|
||||
target triple = "hexagon"
|
||||
|
||||
define void @fred(i64 %a0, i64 %a1, i64 %a2, i64* nocapture %a3, i32 %a4) local_unnamed_addr #0 {
|
||||
b5:
|
||||
%v6 = icmp sgt i32 %a4, 0
|
||||
br i1 %v6, label %b7, label %b20
|
||||
|
||||
b7: ; preds = %b7, %b5
|
||||
%v8 = phi i64* [ %v16, %b7 ], [ %a3, %b5 ]
|
||||
%v9 = phi i32 [ %v18, %b7 ], [ 0, %b5 ]
|
||||
%v10 = phi i64 [ %v17, %b7 ], [ %a0, %b5 ]
|
||||
%v11 = tail call i64 @llvm.hexagon.A2.andp(i64 %v10, i64 1085102592571150095)
|
||||
%v12 = tail call i32 @llvm.hexagon.A2.vcmpbgtu(i64 %a1, i64 %v11)
|
||||
%v13 = tail call i64 @llvm.hexagon.A2.vsubub(i64 %v11, i64 %a1)
|
||||
%v14 = and i32 %v12, 255
|
||||
%v15 = tail call i64 @llvm.hexagon.C2.vmux(i32 %v14, i64 %a2, i64 %v13)
|
||||
store i64 %v15, i64* %v8, align 8
|
||||
%v16 = getelementptr i64, i64* %v8, i32 1
|
||||
%v17 = load i64, i64* %v16, align 8
|
||||
%v18 = add nuw nsw i32 %v9, 1
|
||||
%v19 = icmp eq i32 %v18, %a4
|
||||
br i1 %v19, label %b20, label %b7
|
||||
|
||||
b20: ; preds = %b7, %b5
|
||||
ret void
|
||||
}
|
||||
|
||||
declare i64 @llvm.hexagon.A2.andp(i64, i64) #1
|
||||
declare i32 @llvm.hexagon.A2.vcmpbgtu(i64, i64) #1
|
||||
declare i64 @llvm.hexagon.A2.vsubub(i64, i64) #1
|
||||
declare i64 @llvm.hexagon.C2.vmux(i32, i64, i64) #1
|
||||
|
||||
attributes #0 = { nounwind "target-cpu"="hexagonv60" }
|
||||
attributes #1 = { nounwind readnone }
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
; RUN: llc -march=hexagon < %s | FileCheck %s
|
||||
;
|
||||
; Split all andp/orp instructions (by boosting the profitability of their
|
||||
; operands, which happen to be word masks).
|
||||
; This should result in a loop with two packets, but we don't generate
|
||||
; post-incremented loads, so we end up with 3 packets.
|
||||
|
||||
; CHECK-LABEL: fred
|
||||
; CHECK: loop0([[LOOP:.LBB[0-9_]+]],
|
||||
; CHECK: [[LOOP]]:
|
||||
; CHECK: {
|
||||
; CHECK: {
|
||||
; Make sure that the 3rd packet only has an add in it.
|
||||
; CHECK: {
|
||||
; CHECK: r[[REG:[0-9]+]] = add(r[[REG]],#16)
|
||||
; CHECK-NOT: {
|
||||
; CHECK: }{{[ \t]*}}:endloop0
|
||||
|
||||
target triple = "hexagon"
|
||||
|
||||
define i32 @fred(i32 %a0, i64* nocapture readonly %a1) local_unnamed_addr #0 {
|
||||
b2:
|
||||
%v3 = bitcast i64* %a1 to i32*
|
||||
%v4 = getelementptr inbounds i32, i32* %v3, i32 1
|
||||
%v5 = load i32, i32* %v3, align 4
|
||||
%v6 = load i32, i32* %v4, align 4
|
||||
%v7 = zext i32 %a0 to i64
|
||||
br label %b8
|
||||
|
||||
b8: ; preds = %b8, %b2
|
||||
%v9 = phi i32 [ %v6, %b2 ], [ %v49, %b8 ]
|
||||
%v10 = phi i32 [ %v5, %b2 ], [ %v48, %b8 ]
|
||||
%v11 = phi i32 [ 2, %b2 ], [ %v45, %b8 ]
|
||||
%v12 = phi i64 [ 0, %b2 ], [ %v46, %b8 ]
|
||||
%v13 = phi i64 [ 0, %b2 ], [ %v47, %b8 ]
|
||||
%v14 = phi i32 [ 0, %b2 ], [ %v33, %b8 ]
|
||||
%v15 = phi i32 [ 0, %b2 ], [ %v40, %b8 ]
|
||||
%v16 = zext i32 %v10 to i64
|
||||
%v17 = or i64 %v12, %v16
|
||||
%v18 = tail call i64 @llvm.hexagon.S4.vxsubaddhr(i64 %v17, i64 %v7)
|
||||
%v19 = zext i32 %v9 to i64
|
||||
%v20 = or i64 %v13, %v19
|
||||
%v21 = tail call i64 @llvm.hexagon.S4.vxsubaddhr(i64 %v20, i64 %v7)
|
||||
%v22 = getelementptr inbounds i32, i32* %v3, i32 %v11
|
||||
%v23 = load i32, i32* %v22, align 4
|
||||
%v24 = or i32 %v11, 1
|
||||
%v25 = getelementptr inbounds i32, i32* %v3, i32 %v24
|
||||
%v26 = load i32, i32* %v25, align 4
|
||||
%v27 = zext i32 %v14 to i64
|
||||
%v28 = shl nuw i64 %v27, 32
|
||||
%v29 = zext i32 %v23 to i64
|
||||
%v30 = or i64 %v28, %v29
|
||||
%v31 = tail call i64 @llvm.hexagon.S4.vxaddsubhr(i64 %v30, i64 %v7)
|
||||
%v32 = lshr i64 %v31, 32
|
||||
%v33 = trunc i64 %v32 to i32
|
||||
%v34 = zext i32 %v15 to i64
|
||||
%v35 = shl nuw i64 %v34, 32
|
||||
%v36 = zext i32 %v26 to i64
|
||||
%v37 = or i64 %v35, %v36
|
||||
%v38 = tail call i64 @llvm.hexagon.S4.vxaddsubhr(i64 %v37, i64 %v7)
|
||||
%v39 = lshr i64 %v38, 32
|
||||
%v40 = trunc i64 %v39 to i32
|
||||
%v41 = add nuw nsw i32 %v11, 2
|
||||
%v42 = getelementptr inbounds i32, i32* %v3, i32 %v41
|
||||
%v43 = add nuw nsw i32 %v11, 3
|
||||
%v44 = getelementptr inbounds i32, i32* %v3, i32 %v43
|
||||
%v45 = add nuw nsw i32 %v11, 4
|
||||
%v46 = and i64 %v18, -4294967296
|
||||
%v47 = and i64 %v21, -4294967296
|
||||
%v48 = load i32, i32* %v42, align 4
|
||||
%v49 = load i32, i32* %v44, align 4
|
||||
%v50 = icmp ult i32 %v45, 30
|
||||
br i1 %v50, label %b8, label %b51
|
||||
|
||||
b51: ; preds = %b8
|
||||
%v52 = zext i32 %v48 to i64
|
||||
%v53 = or i64 %v46, %v52
|
||||
%v54 = add i64 %v53, %v7
|
||||
%v55 = lshr i64 %v54, 32
|
||||
%v56 = trunc i64 %v55 to i32
|
||||
%v57 = zext i32 %v49 to i64
|
||||
%v58 = or i64 %v47, %v57
|
||||
%v59 = add i64 %v58, %v7
|
||||
%v60 = lshr i64 %v59, 32
|
||||
%v61 = trunc i64 %v60 to i32
|
||||
%v62 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v33, i32 %v56)
|
||||
%v63 = lshr i64 %v62, 32
|
||||
%v64 = trunc i64 %v63 to i32
|
||||
%v65 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v40, i32 %v61)
|
||||
%v66 = lshr i64 %v65, 32
|
||||
%v67 = trunc i64 %v66 to i32
|
||||
%v68 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v67, i32 %v64)
|
||||
%v69 = lshr i64 %v68, 32
|
||||
%v70 = trunc i64 %v69 to i32
|
||||
ret i32 %v70
|
||||
}
|
||||
|
||||
declare i64 @llvm.hexagon.S4.vxsubaddhr(i64, i64) #1
|
||||
declare i64 @llvm.hexagon.S4.vxaddsubhr(i64, i64) #1
|
||||
declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1
|
||||
|
||||
attributes #0 = { nounwind readonly "target-cpu"="hexagonv60" }
|
||||
attributes #1 = { nounwind readnone }
|
||||
Loading…
Reference in New Issue