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[NVPTX] Fix inline asm test case to use LLVM IR instead of PTX so it works even when the NVPTX target is not built 

llvm-svn: 184601
This commit is contained in:
Justin Holewinski 2013-06-21 22:39:56 +00:00
parent ef171f24d3
commit bcb9055083
1 changed files with 12 additions and 12 deletions
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24
clang/test/CodeGen/nvptx-inlineasm-ptx.c
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@ -1,5 +1,5 @@
// RUN: %clang_cc1 -triple nvptx-unknown-unknown -O3 -S -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple nvptx64-unknown-unknown -O3 -S -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple nvptx-unknown-unknown -O3 -S -o - %s -emit-llvm | FileCheck %s
// RUN: %clang_cc1 -triple nvptx64-unknown-unknown -O3 -S -o - %s -emit-llvm | FileCheck %s
void constraints() {
char c;
@ -13,28 +13,28 @@ void constraints() {
float f;
double d;
// CHECK: mov.b8 %rc{{[0-9]+}}, %rc{{[0-9]+}}
// CHECK: i8 asm sideeffect "mov.b8 $0, $1;", "=c,c"
asm volatile ("mov.b8 %0, %1;" : "=c"(c) : "c"(c));
// CHECK: mov.b8 %rc{{[0-9]+}}, %rc{{[0-9]+}}
// CHECK: i8 asm sideeffect "mov.b8 $0, $1;", "=c,c"
asm volatile ("mov.b8 %0, %1;" : "=c"(uc) : "c"(uc));
// CHECK: mov.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}
// CHECK: i16 asm sideeffect "mov.b16 $0, $1;", "=h,h"
asm volatile ("mov.b16 %0, %1;" : "=h"(s) : "h"(s));
// CHECK: mov.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}
// CHECK: i16 asm sideeffect "mov.b16 $0, $1;", "=h,h"
asm volatile ("mov.b16 %0, %1;" : "=h"(us) : "h"(us));
// CHECK: mov.b32 %r{{[0-9]+}}, %r{{[0-9]+}}
// CHECK: i32 asm sideeffect "mov.b32 $0, $1;", "=r,r"
asm volatile ("mov.b32 %0, %1;" : "=r"(i) : "r"(i));
// CHECK: mov.b32 %r{{[0-9]+}}, %r{{[0-9]+}}
// CHECK: i32 asm sideeffect "mov.b32 $0, $1;", "=r,r"
asm volatile ("mov.b32 %0, %1;" : "=r"(ui) : "r"(ui));
// CHECK: mov.b64 %rl{{[0-9]+}}, %rl{{[0-9]+}}
// CHECK: i64 asm sideeffect "mov.b64 $0, $1;", "=l,l"
asm volatile ("mov.b64 %0, %1;" : "=l"(l) : "l"(l));
// CHECK: mov.b64 %rl{{[0-9]+}}, %rl{{[0-9]+}}
// CHECK: i64 asm sideeffect "mov.b64 $0, $1;", "=l,l"
asm volatile ("mov.b64 %0, %1;" : "=l"(ul) : "l"(ul));
// CHECK: mov.b32 %f{{[0-9]+}}, %f{{[0-9]+}}
// CHECK: float asm sideeffect "mov.b32 $0, $1;", "=f,f"
asm volatile ("mov.b32 %0, %1;" : "=f"(f) : "f"(f));
// CHECK: mov.b64 %fl{{[0-9]+}}, %fl{{[0-9]+}}
// CHECK: double asm sideeffect "mov.b64 $0, $1;", "=d,d"
asm volatile ("mov.b64 %0, %1;" : "=d"(d) : "d"(d));
}