LSR IVChain improvement.
Handle chains in which the same offset is used for both loads and stores to the same array. Fixes rdar://11410078. llvm-svn: 174789
This commit is contained in:
Andrew Trick
parent
58c61e006f
commit
bc7059032b
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@ -2537,6 +2537,7 @@ void LSRInstance::ChainInstruction(Instruction *UserInst, Instruction *IVOper,
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// Add this IV user to the end of the chain.
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IVChainVec[ChainIdx].add(IVInc(UserInst, IVOper, LastIncExpr));
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}
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IVChain &Chain = IVChainVec[ChainIdx];
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SmallPtrSet<Instruction*,4> &NearUsers = ChainUsersVec[ChainIdx].NearUsers;
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// This chain's NearUsers become FarUsers.
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@ -2554,8 +2555,19 @@ void LSRInstance::ChainInstruction(Instruction *UserInst, Instruction *IVOper,
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for (Value::use_iterator UseIter = IVOper->use_begin(),
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UseEnd = IVOper->use_end(); UseIter != UseEnd; ++UseIter) {
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Instruction *OtherUse = dyn_cast<Instruction>(*UseIter);
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if (!OtherUse || OtherUse == UserInst)
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if (!OtherUse)
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continue;
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// Uses in the chain will no longer be uses if the chain is formed.
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// Include the head of the chain in this iteration (not Chain.begin()).
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IVChain::const_iterator IncIter = Chain.Incs.begin();
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IVChain::const_iterator IncEnd = Chain.Incs.end();
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for( ; IncIter != IncEnd; ++IncIter) {
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if (IncIter->UserInst == OtherUse)
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break;
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}
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if (IncIter != IncEnd)
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continue;
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if (SE.isSCEVable(OtherUse->getType())
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&& !isa<SCEVUnknown>(SE.getSCEV(OtherUse))
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&& IU.isIVUserOrOperand(OtherUse)) {
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@ -205,18 +205,18 @@ for.end: ; preds = %for.body
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; post-increment addressing, no add's or add.w's beyond the three
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; mentioned. Most importantly, there should be no spills or reloads!
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;
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; CHECK: testNeon:
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; CHECK: %.lr.ph
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; CHECK-NOT: lsl.w
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; CHECK-NOT: {{ldr|str|adds|add r}}
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; CHECK: add.w r
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; CHECK-NOT: {{ldr|str|adds|add r}}
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; CHECK: add.w r
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; CHECK-NOT: {{ldr|str|adds|add r}}
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; CHECK: add.w r
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; CHECK-NOT: {{ldr|str|adds|add r}}
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; CHECK-NOT: add.w r
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; CHECK: bne
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; A9: testNeon:
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; A9: %.lr.ph
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; A9-NOT: lsl.w
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; A9-NOT: {{ldr|str|adds|add r}}
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; A9: add.w r
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; A9-NOT: {{ldr|str|adds|add r}}
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; A9: add.w r
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; A9-NOT: {{ldr|str|adds|add r}}
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; A9: add.w r
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; A9-NOT: {{ldr|str|adds|add r}}
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; A9-NOT: add.w r
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; A9: bne
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define hidden void @testNeon(i8* %ref_data, i32 %ref_stride, i32 %limit, <16 x i8>* nocapture %data) nounwind optsize {
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%1 = icmp sgt i32 %limit, 0
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br i1 %1, label %.lr.ph, label %45
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@ -290,3 +290,80 @@ define hidden void @testNeon(i8* %ref_data, i32 %ref_stride, i32 %limit, <16 x i
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}
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declare <1 x i64> @llvm.arm.neon.vld1.v1i64(i8*, i32) nounwind readonly
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; Handle chains in which the same offset is used for both loads and
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; stores to the same array.
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; rdar://11410078.
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;
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; A9: @testReuse
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; A9: %for.body
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; A9: vld1.8 {d{{[0-9]+}}}, [[BASE:[r[0-9]+]]], [[INC:r[0-9]]]
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; A9: vld1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]]
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; A9: vld1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]]
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; A9: vld1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]]
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; A9: vld1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]]
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; A9: vld1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]]
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; A9: vld1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]]
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; A9: vld1.8 {d{{[0-9]+}}}, [[BASE]], {{r[0-9]}}
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; A9: vst1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]]
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; A9: vst1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]]
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; A9: vst1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]]
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; A9: vst1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]]
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; A9: vst1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]]
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; A9: vst1.8 {d{{[0-9]+}}}, [[BASE]]
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; A9: bne
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define void @testReuse(i8* %src, i32 %stride) nounwind ssp {
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entry:
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%mul = shl nsw i32 %stride, 2
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%idx.neg = sub i32 0, %mul
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%mul1 = mul nsw i32 %stride, 3
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%idx.neg2 = sub i32 0, %mul1
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%mul5 = shl nsw i32 %stride, 1
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%idx.neg6 = sub i32 0, %mul5
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%idx.neg10 = sub i32 0, %stride
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%i.0110 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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%src.addr = phi i8* [ %src, %entry ], [ %add.ptr45, %for.body ]
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%add.ptr = getelementptr inbounds i8* %src.addr, i32 %idx.neg
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%vld1 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %add.ptr, i32 1)
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%add.ptr3 = getelementptr inbounds i8* %src.addr, i32 %idx.neg2
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%vld2 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %add.ptr3, i32 1)
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%add.ptr7 = getelementptr inbounds i8* %src.addr, i32 %idx.neg6
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%vld3 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %add.ptr7, i32 1)
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%add.ptr11 = getelementptr inbounds i8* %src.addr, i32 %idx.neg10
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%vld4 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %add.ptr11, i32 1)
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%vld5 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %src.addr, i32 1)
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%add.ptr17 = getelementptr inbounds i8* %src.addr, i32 %stride
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%vld6 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %add.ptr17, i32 1)
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%add.ptr20 = getelementptr inbounds i8* %src.addr, i32 %mul5
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%vld7 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %add.ptr20, i32 1)
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%add.ptr23 = getelementptr inbounds i8* %src.addr, i32 %mul1
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%vld8 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %add.ptr23, i32 1)
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%vadd1 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld1, <8 x i8> %vld2) nounwind
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%vadd2 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld2, <8 x i8> %vld3) nounwind
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%vadd3 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld3, <8 x i8> %vld4) nounwind
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%vadd4 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld4, <8 x i8> %vld5) nounwind
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%vadd5 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld5, <8 x i8> %vld6) nounwind
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%vadd6 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld6, <8 x i8> %vld7) nounwind
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tail call void @llvm.arm.neon.vst1.v8i8(i8* %add.ptr3, <8 x i8> %vadd1, i32 1)
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tail call void @llvm.arm.neon.vst1.v8i8(i8* %add.ptr7, <8 x i8> %vadd2, i32 1)
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tail call void @llvm.arm.neon.vst1.v8i8(i8* %add.ptr11, <8 x i8> %vadd3, i32 1)
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tail call void @llvm.arm.neon.vst1.v8i8(i8* %src.addr, <8 x i8> %vadd4, i32 1)
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tail call void @llvm.arm.neon.vst1.v8i8(i8* %add.ptr17, <8 x i8> %vadd5, i32 1)
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tail call void @llvm.arm.neon.vst1.v8i8(i8* %add.ptr20, <8 x i8> %vadd6, i32 1)
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%inc = add nsw i32 %i.0110, 1
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%add.ptr45 = getelementptr inbounds i8* %src.addr, i32 8
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%exitcond = icmp eq i32 %inc, 4
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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ret void
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}
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declare <8 x i8> @llvm.arm.neon.vld1.v8i8(i8*, i32) nounwind readonly
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declare void @llvm.arm.neon.vst1.v8i8(i8*, <8 x i8>, i32) nounwind
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declare <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
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@ -1,4 +1,4 @@
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; RUN: llc < %s | FileCheck %s
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; RUN: opt < %s -loop-reduce -S | FileCheck %s
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;
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; Test LSR's ability to prune formulae that refer to nonexistant
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; AddRecs in other loops.
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@ -15,13 +15,10 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
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target triple = "x86_64-apple-darwin"
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; CHECK: @test
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; CHECK: # %for.body{{$}}
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; dummyiv copy should be removed
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; CHECK-NOT: movq
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; CHECK: # %for.cond19.preheader
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; dummycnt should be removed
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; CHECK-NOT: incq
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; CHECK: # %for.body23{{$}}
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; CHECK: for.body:
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; CHECK: %lsr.iv
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; CHECK-NOT: %dummyout
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; CHECK: ret
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define i64 @test(i64 %count, float* nocapture %srcrow, i32* nocapture %destrow) nounwind uwtable ssp {
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entry:
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%cmp34 = icmp eq i64 %count, 0
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