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[mips] Refactor unconditional branch instruction. Separate encoding information 

from the rest. 

llvm-svn: 170663
This commit is contained in:
Akira Hatanaka 2012-12-20 04:22:39 +00:00
parent e3fbbccc0f
commit bbd197e9c4
2 changed files with 15 additions and 6 deletions
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11
llvm/lib/Target/Mips/MipsInstrFormats.td
View File

@ -279,6 +279,17 @@ class BGEZ_FM<bits<6> op, bits<5> funct> {
let Inst{15-0} = offset;
}
class B_FM {
bits<16> offset;
bits<32> Inst;
let Inst{31-26} = 4;
let Inst{25-21} = 0;
let Inst{20-16} = 0;
let Inst{15-0} = offset;
}
//===----------------------------------------------------------------------===//
//
// FLOATING POINT INSTRUCTION FORMATS

10
llvm/lib/Target/Mips/MipsInstrInfo.td
View File

@ -596,11 +596,9 @@ class JumpFJ<bits<6> op, DAGOperand opnd, string instr_asm,
}
// Unconditional branch
class UncondBranch<bits<6> op, string instr_asm>:
BranchBase<op, (outs), (ins brtarget:$imm16),
!strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> {
let rs = 0;
let rt = 0;
class UncondBranch<string opstr> :
InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
[(br bb:$offset)], IIBranch, FrmI> {
let isBranch = 1;
let isTerminator = 1;
let isBarrier = 1;
@ -979,7 +977,7 @@ def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>,
def J : JumpFJ<0x02, jmptarget, "j", br, bb>,
Requires<[RelocStatic, HasStdEnc]>, IsBranch;
def JR : IndirectBranch<CPURegs>;
def B : UncondBranch<0x04, "b">;
def B : UncondBranch<"b">, B_FM;
def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>;
def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>;
def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>;