parent
b2f17d1719
commit
bb8a40fdd2
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@ -1768,7 +1768,7 @@ ExpandBVWithShuffles(SDNode *Node, SelectionDAG &DAG,
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SmallVector<int, 16> FinalIndices;
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FinalIndices.reserve(IntermedVals[i].second.size() +
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IntermedVals[i+1].second.size());
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int k = 0;
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for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
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++j, ++k) {
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@ -2272,7 +2272,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0,
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EVT DestVT,
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const SDLoc &dl) {
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// TODO: Should any fast-math-flags be set for the created nodes?
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if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
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// simple 32-bit [signed|unsigned] integer to float/double expansion
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@ -2572,7 +2572,7 @@ SDValue SelectionDAGLegalize::ExpandBITREVERSE(SDValue Op, const SDLoc &dl) {
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else
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Tmp2 =
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DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(I - J, dl, SHVT));
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APInt Shift(Sz, 1);
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Shift = Shift.shl(J);
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Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Shift, dl, VT));
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@ -3151,7 +3151,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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Results.push_back(Tmp1);
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break;
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}
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case ISD::FSIN:
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case ISD::FCOS: {
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EVT VT = Node->getValueType(0);
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