diff --git a/llvm/include/llvm/CodeGen/TargetPassConfig.h b/llvm/include/llvm/CodeGen/TargetPassConfig.h index 16cbc1e65032..1aaa85d77a54 100644 --- a/llvm/include/llvm/CodeGen/TargetPassConfig.h +++ b/llvm/include/llvm/CodeGen/TargetPassConfig.h @@ -21,10 +21,10 @@ namespace llvm { +class LLVMTargetMachine; struct MachineSchedContext; class PassConfigImpl; class ScheduleDAGInstrs; -class TargetMachine; // The old pass manager infrastructure is hidden in a legacy namespace now. namespace legacy { @@ -121,7 +121,7 @@ private: void setStartStopPasses(); protected: - TargetMachine *TM; + LLVMTargetMachine *TM; PassConfigImpl *Impl = nullptr; // Internal data structures bool Initialized = false; // Flagged after all passes are configured. @@ -141,7 +141,7 @@ protected: bool addCoreISelPasses(); public: - TargetPassConfig(TargetMachine &TM, PassManagerBase &pm); + TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm); // Dummy constructor. TargetPassConfig(); @@ -378,6 +378,7 @@ protected: virtual void addFastRegAlloc(FunctionPass *RegAllocPass); /// addOptimizedRegAlloc - Add passes related to register allocation. + /// LLVMTargetMachine provides standard regalloc passes for most targets. virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass); /// addPreRewrite - Add passes to the optimized register allocation pipeline diff --git a/llvm/include/llvm/MC/MCAsmInfo.h b/llvm/include/llvm/MC/MCAsmInfo.h index 345dca09be64..234762f36dd4 100644 --- a/llvm/include/llvm/MC/MCAsmInfo.h +++ b/llvm/include/llvm/MC/MCAsmInfo.h @@ -353,7 +353,7 @@ protected: /// The integrated assembler should be enabled by default (by the /// constructors) when failing to parse a valid piece of assembly (inline /// or otherwise) is considered a bug. It may then be overridden after - /// construction (see TargetMachine::initAsmInfo()). + /// construction (see LLVMTargetMachine::initAsmInfo()). bool UseIntegratedAssembler; /// Preserve Comments in assembly diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h index ee7b36b98413..5421b22462ae 100644 --- a/llvm/include/llvm/Target/TargetMachine.h +++ b/llvm/include/llvm/Target/TargetMachine.h @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -/// \file Defines the TargetMachine interface. +// This file defines the TargetMachine and LLVMTargetMachine classes. // //===----------------------------------------------------------------------===// @@ -49,16 +49,16 @@ class PassManagerBase; using legacy::PassManagerBase; //===----------------------------------------------------------------------===// - +/// /// Primary interface to the complete machine description for the target /// machine. All target-specific information should be accessible through this /// interface. +/// class TargetMachine { protected: // Can only create subclasses. TargetMachine(const Target &T, StringRef DataLayoutString, const Triple &TargetTriple, StringRef CPU, StringRef FS, - const TargetOptions &Options, Reloc::Model RM, - CodeModel::Model CM, CodeGenOpt::Level OL); + const TargetOptions &Options); /// The Target that this machine was created for. const Target &TheTarget; @@ -91,8 +91,6 @@ protected: // Can only create subclasses. unsigned RequireStructuredCFG : 1; unsigned O0WantsFastISel : 1; - void initAsmInfo(); - public: const TargetOptions DefaultOptions; mutable TargetOptions Options; @@ -227,18 +225,23 @@ public: /// supported, or false on success. /// \p MMI is an optional parameter that, if set to non-nullptr, /// will be used to set the MachineModuloInfo for this PM. - virtual bool addPassesToEmitFile(PassManagerBase &PM, raw_pwrite_stream &Out, - CodeGenFileType FileType, - bool DisableVerify = true, - MachineModuleInfo *MMI = nullptr); + virtual bool addPassesToEmitFile(PassManagerBase &, raw_pwrite_stream &, + CodeGenFileType, + bool /*DisableVerify*/ = true, + MachineModuleInfo *MMI = nullptr) { + return true; + } /// Add passes to the specified pass manager to get machine code emitted with /// the MCJIT. This method returns true if machine code is not supported. It /// fills the MCContext Ctx pointer which can be used to build custom /// MCStreamer. - virtual bool addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx, - raw_pwrite_stream &OS, - bool DisableVerify = true); + /// + virtual bool addPassesToEmitMC(PassManagerBase &, MCContext *&, + raw_pwrite_stream &, + bool /*DisableVerify*/ = true) { + return true; + } /// True if subtarget inserts the final scheduling pass on its own. /// @@ -262,11 +265,47 @@ public: virtual bool useIPRA() const { return false; } +}; + +/// This class describes a target machine that is implemented with the LLVM +/// target-independent code generator. +/// +class LLVMTargetMachine : public TargetMachine { +protected: // Can only create subclasses. + LLVMTargetMachine(const Target &T, StringRef DataLayoutString, + const Triple &TargetTriple, StringRef CPU, StringRef FS, + const TargetOptions &Options, Reloc::Model RM, + CodeModel::Model CM, CodeGenOpt::Level OL); + + void initAsmInfo(); + +public: + /// \brief Get a TargetIRAnalysis implementation for the target. + /// + /// This analysis will produce a TTI result which uses the common code + /// generator to answer queries about the IR. + TargetIRAnalysis getTargetIRAnalysis() override; /// Create a pass configuration object to be used by addPassToEmitX methods /// for generating a pipeline of CodeGen passes. virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); + /// Add passes to the specified pass manager to get the specified file + /// emitted. Typically this will involve several steps of code generation. + /// \p MMI is an optional parameter that, if set to non-nullptr, + /// will be used to set the MachineModuloInfofor this PM. + bool addPassesToEmitFile(PassManagerBase &PM, raw_pwrite_stream &Out, + CodeGenFileType FileType, bool DisableVerify = true, + MachineModuleInfo *MMI = nullptr) override; + + /// Add passes to the specified pass manager to get machine code emitted with + /// the MCJIT. This method returns true if machine code is not supported. It + /// fills the MCContext Ctx pointer which can be used to build custom + /// MCStreamer. + bool addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx, + raw_pwrite_stream &OS, + bool DisableVerify = true) override; + /// Returns true if the target is expected to pass all machine verifier /// checks. This is a stopgap measure to fix targets one by one. We will /// remove this at some point and always enable the verifier when diff --git a/llvm/lib/CodeGen/CMakeLists.txt b/llvm/lib/CodeGen/CMakeLists.txt index f4949a7abe7a..7ec7fda4e445 100644 --- a/llvm/lib/CodeGen/CMakeLists.txt +++ b/llvm/lib/CodeGen/CMakeLists.txt @@ -53,6 +53,7 @@ add_llvm_library(LLVMCodeGen LiveRegUnits.cpp LiveStackAnalysis.cpp LiveVariables.cpp + LLVMTargetMachine.cpp LocalStackSlotAllocation.cpp LowLevelType.cpp LowerEmuTLS.cpp @@ -141,8 +142,6 @@ add_llvm_library(LLVMCodeGen TargetInstrInfo.cpp TargetLoweringBase.cpp TargetLoweringObjectFileImpl.cpp - TargetMachine.cpp - TargetMachineC.cpp TargetOptionsImpl.cpp TargetPassConfig.cpp TargetRegisterInfo.cpp diff --git a/llvm/lib/CodeGen/TargetMachine.cpp b/llvm/lib/CodeGen/LLVMTargetMachine.cpp similarity index 52% rename from llvm/lib/CodeGen/TargetMachine.cpp rename to llvm/lib/CodeGen/LLVMTargetMachine.cpp index e789273753f0..e829409f0974 100644 --- a/llvm/lib/CodeGen/TargetMachine.cpp +++ b/llvm/lib/CodeGen/LLVMTargetMachine.cpp @@ -1,4 +1,4 @@ -//===-- TargetMachine.cpp - Implement the TargetMachine class -------------===// +//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===// // // The LLVM Compiler Infrastructure // @@ -7,12 +7,10 @@ // //===----------------------------------------------------------------------===// // -/// \file Implements the TargetMachine class. +// This file implements the LLVMTargetMachine class. // //===----------------------------------------------------------------------===// -#include "llvm/Target/TargetMachine.h" - #include "llvm/Analysis/Passes.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/BasicTTIImpl.h" @@ -21,7 +19,6 @@ #include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/IR/IRPrintingPasses.h" #include "llvm/IR/LegacyPassManager.h" -#include "llvm/IR/Mangler.h" #include "llvm/IR/Verifier.h" #include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCAsmInfo.h" @@ -35,187 +32,12 @@ #include "llvm/Support/FormattedStream.h" #include "llvm/Support/TargetRegistry.h" #include "llvm/Target/TargetLoweringObjectFile.h" +#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Transforms/Scalar.h" using namespace llvm; -TargetMachine::TargetMachine(const Target &T, StringRef DataLayoutString, - const Triple &TT, StringRef CPU, StringRef FS, - const TargetOptions &Options, Reloc::Model RM, - CodeModel::Model CM, CodeGenOpt::Level OL) - : TheTarget(T), DL(DataLayoutString), TargetTriple(TT), TargetCPU(CPU), - TargetFS(FS), RM(RM), CMModel(CM), OptLevel(OL), AsmInfo(nullptr), - MRI(nullptr), MII(nullptr), STI(nullptr), RequireStructuredCFG(false), - DefaultOptions(Options), Options(Options) { -} - -TargetMachine::~TargetMachine() { - delete AsmInfo; - delete MRI; - delete MII; - delete STI; -} - -bool TargetMachine::isPositionIndependent() const { - return getRelocationModel() == Reloc::PIC_; -} - -// FIXME: This function needs to go away for a number of reasons: -// a) global state on the TargetMachine is terrible in general, -// b) these target options should be passed only on the function -// and not on the TargetMachine (via TargetOptions) at all. -void TargetMachine::resetTargetOptions(const Function &F) const { -#define RESET_OPTION(X, Y) \ - do { \ - if (F.hasFnAttribute(Y)) \ - Options.X = (F.getFnAttribute(Y).getValueAsString() == "true"); \ - else \ - Options.X = DefaultOptions.X; \ - } while (0) - - RESET_OPTION(UnsafeFPMath, "unsafe-fp-math"); - RESET_OPTION(NoInfsFPMath, "no-infs-fp-math"); - RESET_OPTION(NoNaNsFPMath, "no-nans-fp-math"); - RESET_OPTION(NoSignedZerosFPMath, "no-signed-zeros-fp-math"); - RESET_OPTION(NoTrappingFPMath, "no-trapping-math"); - - StringRef Denormal = - F.getFnAttribute("denormal-fp-math").getValueAsString(); - if (Denormal == "ieee") - Options.FPDenormalMode = FPDenormal::IEEE; - else if (Denormal == "preserve-sign") - Options.FPDenormalMode = FPDenormal::PreserveSign; - else if (Denormal == "positive-zero") - Options.FPDenormalMode = FPDenormal::PositiveZero; - else - Options.FPDenormalMode = DefaultOptions.FPDenormalMode; -} - -Reloc::Model TargetMachine::getRelocationModel() const { return RM; } - -CodeModel::Model TargetMachine::getCodeModel() const { return CMModel; } - -/// Get the IR-specified TLS model for Var. -static TLSModel::Model getSelectedTLSModel(const GlobalValue *GV) { - switch (GV->getThreadLocalMode()) { - case GlobalVariable::NotThreadLocal: - llvm_unreachable("getSelectedTLSModel for non-TLS variable"); - break; - case GlobalVariable::GeneralDynamicTLSModel: - return TLSModel::GeneralDynamic; - case GlobalVariable::LocalDynamicTLSModel: - return TLSModel::LocalDynamic; - case GlobalVariable::InitialExecTLSModel: - return TLSModel::InitialExec; - case GlobalVariable::LocalExecTLSModel: - return TLSModel::LocalExec; - } - llvm_unreachable("invalid TLS model"); -} - -bool TargetMachine::shouldAssumeDSOLocal(const Module &M, - const GlobalValue *GV) const { - Reloc::Model RM = getRelocationModel(); - const Triple &TT = getTargetTriple(); - - // DLLImport explicitly marks the GV as external. - if (GV && GV->hasDLLImportStorageClass()) - return false; - - // Every other GV is local on COFF. - // Make an exception for windows OS in the triple: Some firmwares builds use - // *-win32-macho triples. This (accidentally?) produced windows relocations - // without GOT tables in older clang versions; Keep this behaviour. - if (TT.isOSBinFormatCOFF() || (TT.isOSWindows() && TT.isOSBinFormatMachO())) - return true; - - if (GV && (GV->hasLocalLinkage() || !GV->hasDefaultVisibility())) - return true; - - if (TT.isOSBinFormatMachO()) { - if (RM == Reloc::Static) - return true; - return GV && GV->isStrongDefinitionForLinker(); - } - - assert(TT.isOSBinFormatELF()); - assert(RM != Reloc::DynamicNoPIC); - - bool IsExecutable = - RM == Reloc::Static || M.getPIELevel() != PIELevel::Default; - if (IsExecutable) { - // If the symbol is defined, it cannot be preempted. - if (GV && !GV->isDeclarationForLinker()) - return true; - - bool IsTLS = GV && GV->isThreadLocal(); - bool IsAccessViaCopyRelocs = Options.MCOptions.MCPIECopyRelocations && GV && - isa(GV) && - !GV->hasExternalWeakLinkage(); - Triple::ArchType Arch = TT.getArch(); - bool IsPPC = - Arch == Triple::ppc || Arch == Triple::ppc64 || Arch == Triple::ppc64le; - // Check if we can use copy relocations. PowerPC has no copy relocations. - if (!IsTLS && !IsPPC && (RM == Reloc::Static || IsAccessViaCopyRelocs)) - return true; - } - - // ELF supports preemption of other symbols. - return false; -} - -TLSModel::Model TargetMachine::getTLSModel(const GlobalValue *GV) const { - bool IsPIE = GV->getParent()->getPIELevel() != PIELevel::Default; - Reloc::Model RM = getRelocationModel(); - bool IsSharedLibrary = RM == Reloc::PIC_ && !IsPIE; - bool IsLocal = shouldAssumeDSOLocal(*GV->getParent(), GV); - - TLSModel::Model Model; - if (IsSharedLibrary) { - if (IsLocal) - Model = TLSModel::LocalDynamic; - else - Model = TLSModel::GeneralDynamic; - } else { - if (IsLocal) - Model = TLSModel::LocalExec; - else - Model = TLSModel::InitialExec; - } - - // If the user specified a more specific model, use that. - TLSModel::Model SelectedModel = getSelectedTLSModel(GV); - if (SelectedModel > Model) - return SelectedModel; - - return Model; -} - -CodeGenOpt::Level TargetMachine::getOptLevel() const { return OptLevel; } - -void TargetMachine::setOptLevel(CodeGenOpt::Level Level) { OptLevel = Level; } - -void TargetMachine::getNameWithPrefix(SmallVectorImpl &Name, - const GlobalValue *GV, Mangler &Mang, - bool MayAlwaysUsePrivate) const { - if (MayAlwaysUsePrivate || !GV->hasPrivateLinkage()) { - // Simple case: If GV is not private, it is not important to find out if - // private labels are legal in this case or not. - Mang.getNameWithPrefix(Name, GV, false); - return; - } - const TargetLoweringObjectFile *TLOF = getObjFileLowering(); - TLOF->getNameWithPrefix(Name, GV, *this); -} - -MCSymbol *TargetMachine::getSymbol(const GlobalValue *GV) const { - const TargetLoweringObjectFile *TLOF = getObjFileLowering(); - SmallString<128> NameStr; - getNameWithPrefix(NameStr, GV, TLOF->getMangler()); - return TLOF->getContext().getOrCreateSymbol(NameStr); -} - -void TargetMachine::initAsmInfo() { +void LLVMTargetMachine::initAsmInfo() { MRI = TheTarget.createMCRegInfo(getTargetTriple().str()); MII = TheTarget.createMCInstrInfo(); // FIXME: Having an MCSubtargetInfo on the target machine is a hack due @@ -250,7 +72,19 @@ void TargetMachine::initAsmInfo() { AsmInfo = TmpAsmInfo; } -TargetIRAnalysis TargetMachine::getTargetIRAnalysis() { +LLVMTargetMachine::LLVMTargetMachine(const Target &T, + StringRef DataLayoutString, + const Triple &TT, StringRef CPU, + StringRef FS, const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL) + : TargetMachine(T, DataLayoutString, TT, CPU, FS, Options) { + this->RM = RM; + this->CMModel = CM; + this->OptLevel = OL; +} + +TargetIRAnalysis LLVMTargetMachine::getTargetIRAnalysis() { return TargetIRAnalysis([this](const Function &F) { return TargetTransformInfo(BasicTTIImpl(this, F)); }); @@ -258,7 +92,7 @@ TargetIRAnalysis TargetMachine::getTargetIRAnalysis() { /// addPassesToX helper drives creation and initialization of TargetPassConfig. static MCContext * -addPassesToGenerateCode(TargetMachine *TM, PassManagerBase &PM, +addPassesToGenerateCode(LLVMTargetMachine *TM, PassManagerBase &PM, bool DisableVerify, bool &WillCompleteCodeGenPipeline, raw_pwrite_stream &Out, MachineModuleInfo *MMI) { // Targets may override createPassConfig to provide a target-specific @@ -282,7 +116,7 @@ addPassesToGenerateCode(TargetMachine *TM, PassManagerBase &PM, return &MMI->getContext(); } -bool TargetMachine::addAsmPrinter(PassManagerBase &PM, +bool LLVMTargetMachine::addAsmPrinter(PassManagerBase &PM, raw_pwrite_stream &Out, CodeGenFileType FileType, MCContext &Context) { if (Options.MCOptions.MCSaveTempLabels) @@ -354,11 +188,11 @@ bool TargetMachine::addAsmPrinter(PassManagerBase &PM, return false; } -bool TargetMachine::addPassesToEmitFile(PassManagerBase &PM, - raw_pwrite_stream &Out, - CodeGenFileType FileType, - bool DisableVerify, - MachineModuleInfo *MMI) { +bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, + raw_pwrite_stream &Out, + CodeGenFileType FileType, + bool DisableVerify, + MachineModuleInfo *MMI) { // Add common CodeGen passes. bool WillCompleteCodeGenPipeline = true; MCContext *Context = addPassesToGenerateCode( @@ -373,9 +207,14 @@ bool TargetMachine::addPassesToEmitFile(PassManagerBase &PM, return false; } -bool TargetMachine::addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx, - raw_pwrite_stream &Out, - bool DisableVerify) { +/// addPassesToEmitMC - Add passes to the specified pass manager to get +/// machine code emitted with the MCJIT. This method returns true if machine +/// code is not supported. It fills the MCContext Ctx pointer which can be +/// used to build custom MCStreamer. +/// +bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx, + raw_pwrite_stream &Out, + bool DisableVerify) { // Add common CodeGen passes. bool WillCompleteCodeGenPipeline = true; Ctx = addPassesToGenerateCode(this, PM, DisableVerify, diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 3cfc800f0b13..0bd5c56871ca 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -17,8 +17,10 @@ // Register live intervals: Registers must be defined only once, and must be // defined before use. // -// The machine code verifier is enabled with the command-line option -// -verify-machineinstrs. +// The machine code verifier is enabled from LLVMTargetMachine.cpp with the +// command-line option -verify-machineinstrs, or by defining the environment +// variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive +// the verifier errors. //===----------------------------------------------------------------------===// #include "llvm/ADT/BitVector.h" diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp index 0f6d152cee9c..c5101b1ecfc2 100644 --- a/llvm/lib/CodeGen/TargetPassConfig.cpp +++ b/llvm/lib/CodeGen/TargetPassConfig.cpp @@ -355,7 +355,7 @@ void TargetPassConfig::setStartStopPasses() { // Out of line constructor provides default values for pass options and // registers all common codegen passes. -TargetPassConfig::TargetPassConfig(TargetMachine &TM, PassManagerBase &pm) +TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm) : ImmutablePass(ID), PM(&pm), TM(&TM) { Impl = new PassConfigImpl(); @@ -408,7 +408,7 @@ void TargetPassConfig::insertPass(AnalysisID TargetPassID, /// addPassToEmitX methods for generating a pipeline of CodeGen passes. /// /// Targets may override this to extend TargetPassConfig. -TargetPassConfig *TargetMachine::createPassConfig(PassManagerBase &PM) { +TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) { return new TargetPassConfig(*this, PM); } diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp index 882065edab4b..1762475ac93f 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -237,9 +237,10 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT, Optional CM, CodeGenOpt::Level OL, bool JIT, bool LittleEndian) - : TargetMachine(T, computeDataLayout(TT, Options.MCOptions, LittleEndian), - TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM), - getEffectiveCodeModel(TT, CM, JIT), OL), + : LLVMTargetMachine(T, + computeDataLayout(TT, Options.MCOptions, LittleEndian), + TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM), + getEffectiveCodeModel(TT, CM, JIT), OL), TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) { initAsmInfo(); } diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.h b/llvm/lib/Target/AArch64/AArch64TargetMachine.h index fb41e3c9645e..2bbfb2da3db6 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.h +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.h @@ -23,7 +23,7 @@ namespace llvm { class AArch64RegisterBankInfo; -class AArch64TargetMachine : public TargetMachine { +class AArch64TargetMachine : public LLVMTargetMachine { protected: std::unique_ptr TLOF; mutable StringMap> SubtargetMap; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 54d43d403c5e..f20dba844d31 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -290,9 +290,9 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT, Optional RM, Optional CM, CodeGenOpt::Level OptLevel) - : TargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU), - FS, Options, getEffectiveRelocModel(RM), - getEffectiveCodeModel(CM), OptLevel), + : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU), + FS, Options, getEffectiveRelocModel(RM), + getEffectiveCodeModel(CM), OptLevel), TLOF(createTLOF(getTargetTriple())) { AS = AMDGPU::getAMDGPUAS(TT); initAsmInfo(); @@ -471,7 +471,7 @@ namespace { class AMDGPUPassConfig : public TargetPassConfig { public: - AMDGPUPassConfig(TargetMachine &TM, PassManagerBase &PM) + AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM) : TargetPassConfig(TM, PM) { // Exceptions and StackMaps are not supported, so these passes will never do // anything. @@ -502,7 +502,7 @@ public: class R600PassConfig final : public AMDGPUPassConfig { public: - R600PassConfig(TargetMachine &TM, PassManagerBase &PM) + R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM) : AMDGPUPassConfig(TM, PM) {} ScheduleDAGInstrs *createMachineScheduler( @@ -519,7 +519,7 @@ public: class GCNPassConfig final : public AMDGPUPassConfig { public: - GCNPassConfig(TargetMachine &TM, PassManagerBase &PM) + GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM) : AMDGPUPassConfig(TM, PM) { // It is necessary to know the register usage of the entire call graph. We // allow calls without EnableAMDGPUFunctionCalls if they are marked diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h index 770c0977bdb5..34114bf73bce 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h @@ -31,7 +31,7 @@ namespace llvm { // AMDGPU Target Machine (R600+) //===----------------------------------------------------------------------===// -class AMDGPUTargetMachine : public TargetMachine { +class AMDGPUTargetMachine : public LLVMTargetMachine { protected: std::unique_ptr TLOF; AMDGPUIntrinsicInfo IntrinsicInfo; diff --git a/llvm/lib/Target/ARC/ARCTargetMachine.cpp b/llvm/lib/Target/ARC/ARCTargetMachine.cpp index 65f3ce0e45dc..d2512c281a61 100644 --- a/llvm/lib/Target/ARC/ARCTargetMachine.cpp +++ b/llvm/lib/Target/ARC/ARCTargetMachine.cpp @@ -39,10 +39,11 @@ ARCTargetMachine::ARCTargetMachine(const Target &T, const Triple &TT, Optional RM, Optional CM, CodeGenOpt::Level OL, bool JIT) - : TargetMachine(T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" - "f32:32:32-i64:32-f64:32-a:0:32-n32", - TT, CPU, FS, Options, getRelocModel(RM), - getEffectiveCodeModel(CM), OL), + : LLVMTargetMachine(T, + "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" + "f32:32:32-i64:32-f64:32-a:0:32-n32", + TT, CPU, FS, Options, getRelocModel(RM), + getEffectiveCodeModel(CM), OL), TLOF(make_unique()), Subtarget(TT, CPU, FS, *this) { initAsmInfo(); diff --git a/llvm/lib/Target/ARC/ARCTargetMachine.h b/llvm/lib/Target/ARC/ARCTargetMachine.h index df911b537b88..98021b3dc1d5 100644 --- a/llvm/lib/Target/ARC/ARCTargetMachine.h +++ b/llvm/lib/Target/ARC/ARCTargetMachine.h @@ -21,7 +21,7 @@ namespace llvm { class TargetPassConfig; -class ARCTargetMachine : public TargetMachine { +class ARCTargetMachine : public LLVMTargetMachine { std::unique_ptr TLOF; ARCSubtarget Subtarget; diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp index bc8f299db564..9a191e422477 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -205,9 +205,9 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT, Optional RM, Optional CM, CodeGenOpt::Level OL, bool isLittle) - : TargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, - CPU, FS, Options, getEffectiveRelocModel(TT, RM), - getEffectiveCodeModel(CM), OL), + : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, + CPU, FS, Options, getEffectiveRelocModel(TT, RM), + getEffectiveCodeModel(CM), OL), TargetABI(computeTargetABI(TT, CPU, Options)), TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) { diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.h b/llvm/lib/Target/ARM/ARMTargetMachine.h index dcd4f68b644a..655ec3202bfb 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.h +++ b/llvm/lib/Target/ARM/ARMTargetMachine.h @@ -25,7 +25,7 @@ namespace llvm { -class ARMBaseTargetMachine : public TargetMachine { +class ARMBaseTargetMachine : public LLVMTargetMachine { public: enum ARMABI { ARM_ABI_UNKNOWN, diff --git a/llvm/lib/Target/AVR/AVRTargetMachine.cpp b/llvm/lib/Target/AVR/AVRTargetMachine.cpp index 1fbabe00606e..f9a738b2182c 100644 --- a/llvm/lib/Target/AVR/AVRTargetMachine.cpp +++ b/llvm/lib/Target/AVR/AVRTargetMachine.cpp @@ -52,8 +52,9 @@ AVRTargetMachine::AVRTargetMachine(const Target &T, const Triple &TT, Optional RM, Optional CM, CodeGenOpt::Level OL, bool JIT) - : TargetMachine(T, AVRDataLayout, TT, getCPU(CPU), FS, Options, - getEffectiveRelocModel(RM), getEffectiveCodeModel(CM), OL), + : LLVMTargetMachine(T, AVRDataLayout, TT, getCPU(CPU), FS, Options, + getEffectiveRelocModel(RM), getEffectiveCodeModel(CM), + OL), SubTarget(TT, getCPU(CPU), FS, *this) { this->TLOF = make_unique(); initAsmInfo(); diff --git a/llvm/lib/Target/AVR/AVRTargetMachine.h b/llvm/lib/Target/AVR/AVRTargetMachine.h index 123ee31fdb9c..ffcf4350d45a 100644 --- a/llvm/lib/Target/AVR/AVRTargetMachine.h +++ b/llvm/lib/Target/AVR/AVRTargetMachine.h @@ -26,11 +26,12 @@ namespace llvm { /// A generic AVR implementation. -class AVRTargetMachine : public TargetMachine { +class AVRTargetMachine : public LLVMTargetMachine { public: AVRTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional RM, Optional CM, + Optional RM, + Optional CM, CodeGenOpt::Level OL, bool JIT); const AVRSubtarget *getSubtargetImpl() const; diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.cpp b/llvm/lib/Target/BPF/BPFTargetMachine.cpp index 7a189bb85615..60672fa2684b 100644 --- a/llvm/lib/Target/BPF/BPFTargetMachine.cpp +++ b/llvm/lib/Target/BPF/BPFTargetMachine.cpp @@ -55,8 +55,9 @@ BPFTargetMachine::BPFTargetMachine(const Target &T, const Triple &TT, Optional RM, Optional CM, CodeGenOpt::Level OL, bool JIT) - : TargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, - getEffectiveRelocModel(RM), getEffectiveCodeModel(CM), OL), + : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, + getEffectiveRelocModel(RM), getEffectiveCodeModel(CM), + OL), TLOF(make_unique()), Subtarget(TT, CPU, FS, *this) { initAsmInfo(); diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.h b/llvm/lib/Target/BPF/BPFTargetMachine.h index 746d7886a04c..a560dd27335a 100644 --- a/llvm/lib/Target/BPF/BPFTargetMachine.h +++ b/llvm/lib/Target/BPF/BPFTargetMachine.h @@ -18,7 +18,7 @@ #include "llvm/Target/TargetMachine.h" namespace llvm { -class BPFTargetMachine : public TargetMachine { +class BPFTargetMachine : public LLVMTargetMachine { std::unique_ptr TLOF; BPFSubtarget Subtarget; diff --git a/llvm/lib/Target/CMakeLists.txt b/llvm/lib/Target/CMakeLists.txt index c56e04e1a20c..1e6abfacb792 100644 --- a/llvm/lib/Target/CMakeLists.txt +++ b/llvm/lib/Target/CMakeLists.txt @@ -6,6 +6,8 @@ add_llvm_library(LLVMTarget Target.cpp TargetIntrinsicInfo.cpp TargetLoweringObjectFile.cpp + TargetMachine.cpp + TargetMachineC.cpp ADDITIONAL_HEADER_DIRS ${LLVM_MAIN_INCLUDE_DIR}/llvm/Target diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp index 33439a78cb58..7b2774f8c408 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -194,7 +194,7 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT, // Specify the vector alignment explicitly. For v512x1, the calculated // alignment would be 512*alignment(i1), which is 512 bytes, instead of // the required minimum of 64 bytes. - : TargetMachine( + : LLVMTargetMachine( T, "e-m:e-p:32:32:32-a:0-n16:32-" "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h index f91606699499..acd41f920b53 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h @@ -23,7 +23,7 @@ namespace llvm { class Module; -class HexagonTargetMachine : public TargetMachine { +class HexagonTargetMachine : public LLVMTargetMachine { std::unique_ptr TLOF; mutable StringMap> SubtargetMap; diff --git a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp index ec358e9495e4..9a73c95d6516 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp +++ b/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp @@ -65,9 +65,9 @@ LanaiTargetMachine::LanaiTargetMachine(const Target &T, const Triple &TT, Optional RM, Optional CodeModel, CodeGenOpt::Level OptLevel, bool JIT) - : TargetMachine(T, computeDataLayout(), TT, Cpu, FeatureString, Options, - getEffectiveRelocModel(RM), - getEffectiveCodeModel(CodeModel), OptLevel), + : LLVMTargetMachine(T, computeDataLayout(), TT, Cpu, FeatureString, Options, + getEffectiveRelocModel(RM), + getEffectiveCodeModel(CodeModel), OptLevel), Subtarget(TT, Cpu, FeatureString, *this, Options, getCodeModel(), OptLevel), TLOF(new LanaiTargetObjectFile()) { diff --git a/llvm/lib/Target/Lanai/LanaiTargetMachine.h b/llvm/lib/Target/Lanai/LanaiTargetMachine.h index 5f12bd3c827f..ce1271d9deaa 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetMachine.h +++ b/llvm/lib/Target/Lanai/LanaiTargetMachine.h @@ -25,7 +25,7 @@ namespace llvm { class formatted_raw_ostream; -class LanaiTargetMachine : public TargetMachine { +class LanaiTargetMachine : public LLVMTargetMachine { LanaiSubtarget Subtarget; std::unique_ptr TLOF; diff --git a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp index 44f16941d6eb..01f44e266d7b 100644 --- a/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp +++ b/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp @@ -49,9 +49,9 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T, const Triple &TT, Optional RM, Optional CM, CodeGenOpt::Level OL, bool JIT) - : TargetMachine(T, computeDataLayout(TT, CPU, Options), TT, CPU, FS, - Options, getEffectiveRelocModel(RM), - getEffectiveCodeModel(CM), OL), + : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options), TT, CPU, FS, + Options, getEffectiveRelocModel(RM), + getEffectiveCodeModel(CM), OL), TLOF(make_unique()), Subtarget(TT, CPU, FS, *this) { initAsmInfo(); diff --git a/llvm/lib/Target/MSP430/MSP430TargetMachine.h b/llvm/lib/Target/MSP430/MSP430TargetMachine.h index bd32004b9804..97b5e810a1d3 100644 --- a/llvm/lib/Target/MSP430/MSP430TargetMachine.h +++ b/llvm/lib/Target/MSP430/MSP430TargetMachine.h @@ -23,7 +23,7 @@ namespace llvm { /// MSP430TargetMachine /// -class MSP430TargetMachine : public TargetMachine { +class MSP430TargetMachine : public LLVMTargetMachine { std::unique_ptr TLOF; MSP430Subtarget Subtarget; diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp index 0aa41141b0a8..f01a800afc5e 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp @@ -686,7 +686,7 @@ MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S, MCAssembler &MCA = getStreamer().getAssembler(); // It's possible that MCObjectFileInfo isn't fully initialized at this point - // due to an initialization order problem where TargetMachine creates the + // due to an initialization order problem where LLVMTargetMachine creates the // target streamer before TargetLoweringObjectFile calls // InitializeMCObjectFileInfo. There doesn't seem to be a single place that // covers all cases so this statement covers most cases and direct object diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp index 179971bbc191..6199ffd789c3 100644 --- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp +++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp @@ -109,9 +109,9 @@ MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT, Optional CM, CodeGenOpt::Level OL, bool JIT, bool isLittle) - : TargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, - CPU, FS, Options, getEffectiveRelocModel(JIT, RM), - getEffectiveCodeModel(CM), OL), + : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, + CPU, FS, Options, getEffectiveRelocModel(JIT, RM), + getEffectiveCodeModel(CM), OL), isLittle(isLittle), TLOF(llvm::make_unique()), ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)), Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this, diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.h b/llvm/lib/Target/Mips/MipsTargetMachine.h index 20627c31ffd7..ccfc9a938d9c 100644 --- a/llvm/lib/Target/Mips/MipsTargetMachine.h +++ b/llvm/lib/Target/Mips/MipsTargetMachine.h @@ -25,7 +25,7 @@ namespace llvm { -class MipsTargetMachine : public TargetMachine { +class MipsTargetMachine : public LLVMTargetMachine { bool isLittle; std::unique_ptr TLOF; // Selected ABI diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp index 393d256883b0..85f757878f94 100644 --- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -100,8 +100,8 @@ NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT, CodeGenOpt::Level OL, bool is64bit) // The pic relocation model is used regardless of what the client has // specified, as it is the only relocation model currently supported. - : TargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, - Reloc::PIC_, getEffectiveCodeModel(CM), OL), + : LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, + Reloc::PIC_, getEffectiveCodeModel(CM), OL), is64bit(is64bit), TLOF(llvm::make_unique()), Subtarget(TT, CPU, FS, *this) { if (TT.getOS() == Triple::NVCL) diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h index 8bea331580a9..7674135f0a7c 100644 --- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h +++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h @@ -24,7 +24,7 @@ namespace llvm { /// NVPTXTargetMachine /// -class NVPTXTargetMachine : public TargetMachine { +class NVPTXTargetMachine : public LLVMTargetMachine { bool is64bit; std::unique_ptr TLOF; NVPTX::DrvInterface drvInterface; diff --git a/llvm/lib/Target/Nios2/Nios2TargetMachine.cpp b/llvm/lib/Target/Nios2/Nios2TargetMachine.cpp index 6155d0b6ec87..7370dac2ce38 100644 --- a/llvm/lib/Target/Nios2/Nios2TargetMachine.cpp +++ b/llvm/lib/Target/Nios2/Nios2TargetMachine.cpp @@ -42,8 +42,8 @@ Nios2TargetMachine::Nios2TargetMachine(const Target &T, const Triple &TT, Optional RM, Optional CM, CodeGenOpt::Level OL, bool JIT) - : TargetMachine(T, computeDataLayout(), TT, CPU, FS, Options, - getEffectiveRelocModel(RM), *CM, OL) {} + : LLVMTargetMachine(T, computeDataLayout(), TT, CPU, FS, Options, + getEffectiveRelocModel(RM), *CM, OL) {} Nios2TargetMachine::~Nios2TargetMachine() {} diff --git a/llvm/lib/Target/Nios2/Nios2TargetMachine.h b/llvm/lib/Target/Nios2/Nios2TargetMachine.h index 5412e8749697..503187778c1b 100644 --- a/llvm/lib/Target/Nios2/Nios2TargetMachine.h +++ b/llvm/lib/Target/Nios2/Nios2TargetMachine.h @@ -18,7 +18,7 @@ #include "llvm/Target/TargetMachine.h" namespace llvm { -class Nios2TargetMachine : public TargetMachine { +class Nios2TargetMachine : public LLVMTargetMachine { mutable StringMap> SubtargetMap; public: diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp index eafa877a158b..9e146786469f 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -225,7 +225,7 @@ static CodeModel::Model getEffectiveCodeModel(const Triple &TT, // The FeatureString here is a little subtle. We are modifying the feature // string with what are (currently) non-function specific overrides as it goes -// into the TargetMachine constructor and then using the stored value in the +// into the LLVMTargetMachine constructor and then using the stored value in the // Subtarget constructor below it. PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, @@ -233,10 +233,10 @@ PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT, Optional RM, Optional CM, CodeGenOpt::Level OL, bool JIT) - : TargetMachine(T, getDataLayoutString(TT), TT, CPU, - computeFSAdditions(FS, OL, TT), Options, - getEffectiveRelocModel(TT, RM), - getEffectiveCodeModel(TT, CM, JIT), OL), + : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU, + computeFSAdditions(FS, OL, TT), Options, + getEffectiveRelocModel(TT, RM), + getEffectiveCodeModel(TT, CM, JIT), OL), TLOF(createTLOF(getTargetTriple())), TargetABI(computeTargetABI(TT, Options)) { initAsmInfo(); diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.h b/llvm/lib/Target/PowerPC/PPCTargetMachine.h index d3be1ee605b9..102bf7ca59c2 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.h +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.h @@ -23,7 +23,7 @@ namespace llvm { /// Common code between 32-bit and 64-bit PowerPC targets. /// -class PPCTargetMachine final : public TargetMachine { +class PPCTargetMachine final : public LLVMTargetMachine { public: enum PPCABI { PPC_ABI_UNKNOWN, PPC_ABI_ELFv1, PPC_ABI_ELFv2 }; private: diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index aa67c0ee1db8..78d9cf53b5d6 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -55,9 +55,9 @@ RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT, Optional RM, Optional CM, CodeGenOpt::Level OL, bool JIT) - : TargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, - getEffectiveRelocModel(TT, RM), - getEffectiveCodeModel(CM), OL), + : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, + getEffectiveRelocModel(TT, RM), + getEffectiveCodeModel(CM), OL), TLOF(make_unique()) { initAsmInfo(); } diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.h b/llvm/lib/Target/RISCV/RISCVTargetMachine.h index ea245735ae4f..5c2ec956ee29 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.h +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.h @@ -20,7 +20,7 @@ #include "llvm/Target/TargetMachine.h" namespace llvm { -class RISCVTargetMachine : public TargetMachine { +class RISCVTargetMachine : public LLVMTargetMachine { std::unique_ptr TLOF; public: diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp index b3142c43fd57..a0d40653fd9b 100644 --- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp @@ -88,7 +88,7 @@ SparcTargetMachine::SparcTargetMachine( const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, CodeGenOpt::Level OL, bool JIT, bool is64bit) - : TargetMachine( + : LLVMTargetMachine( T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options, getEffectiveRelocModel(RM), getEffectiveCodeModel(CM, getEffectiveRelocModel(RM), is64bit, JIT), diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.h b/llvm/lib/Target/Sparc/SparcTargetMachine.h index 69f8ba796d03..b0d76abeba7d 100644 --- a/llvm/lib/Target/Sparc/SparcTargetMachine.h +++ b/llvm/lib/Target/Sparc/SparcTargetMachine.h @@ -20,7 +20,7 @@ namespace llvm { -class SparcTargetMachine : public TargetMachine { +class SparcTargetMachine : public LLVMTargetMachine { std::unique_ptr TLOF; SparcSubtarget Subtarget; bool is64Bit; diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp index d3f24c9d9e47..aa76a96413be 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp +++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp @@ -143,7 +143,7 @@ SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT, Optional RM, Optional CM, CodeGenOpt::Level OL, bool JIT) - : TargetMachine( + : LLVMTargetMachine( T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options, getEffectiveRelocModel(RM), getEffectiveCodeModel(CM, getEffectiveRelocModel(RM), JIT), OL), diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h index 723944dbec1c..95ad5e339e0b 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h +++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h @@ -25,7 +25,7 @@ namespace llvm { -class SystemZTargetMachine : public TargetMachine { +class SystemZTargetMachine : public LLVMTargetMachine { std::unique_ptr TLOF; SystemZSubtarget Subtarget; @@ -42,7 +42,7 @@ public: return &Subtarget; } - // Override TargetMachine + // Override LLVMTargetMachine TargetPassConfig *createPassConfig(PassManagerBase &PM) override; TargetIRAnalysis getTargetIRAnalysis() override; diff --git a/llvm/lib/Target/TargetMachine.cpp b/llvm/lib/Target/TargetMachine.cpp new file mode 100644 index 000000000000..3b16dee5a0fa --- /dev/null +++ b/llvm/lib/Target/TargetMachine.cpp @@ -0,0 +1,222 @@ +//===-- TargetMachine.cpp - General Target Information ---------------------==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the general parts of a Target machine. +// +//===----------------------------------------------------------------------===// + +#include "llvm/Target/TargetMachine.h" +#include "llvm/Analysis/TargetTransformInfo.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/IR/Function.h" +#include "llvm/IR/GlobalAlias.h" +#include "llvm/IR/GlobalValue.h" +#include "llvm/IR/GlobalVariable.h" +#include "llvm/IR/LegacyPassManager.h" +#include "llvm/IR/Mangler.h" +#include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCSectionMachO.h" +#include "llvm/MC/MCTargetOptions.h" +#include "llvm/MC/SectionKind.h" +#include "llvm/Target/TargetLowering.h" +#include "llvm/Target/TargetLoweringObjectFile.h" +#include "llvm/Target/TargetSubtargetInfo.h" +using namespace llvm; + +//--------------------------------------------------------------------------- +// TargetMachine Class +// + +TargetMachine::TargetMachine(const Target &T, StringRef DataLayoutString, + const Triple &TT, StringRef CPU, StringRef FS, + const TargetOptions &Options) + : TheTarget(T), DL(DataLayoutString), TargetTriple(TT), TargetCPU(CPU), + TargetFS(FS), AsmInfo(nullptr), MRI(nullptr), MII(nullptr), STI(nullptr), + RequireStructuredCFG(false), DefaultOptions(Options), Options(Options) { +} + +TargetMachine::~TargetMachine() { + delete AsmInfo; + delete MRI; + delete MII; + delete STI; +} + +bool TargetMachine::isPositionIndependent() const { + return getRelocationModel() == Reloc::PIC_; +} + +/// \brief Reset the target options based on the function's attributes. +// FIXME: This function needs to go away for a number of reasons: +// a) global state on the TargetMachine is terrible in general, +// b) these target options should be passed only on the function +// and not on the TargetMachine (via TargetOptions) at all. +void TargetMachine::resetTargetOptions(const Function &F) const { +#define RESET_OPTION(X, Y) \ + do { \ + if (F.hasFnAttribute(Y)) \ + Options.X = (F.getFnAttribute(Y).getValueAsString() == "true"); \ + else \ + Options.X = DefaultOptions.X; \ + } while (0) + + RESET_OPTION(UnsafeFPMath, "unsafe-fp-math"); + RESET_OPTION(NoInfsFPMath, "no-infs-fp-math"); + RESET_OPTION(NoNaNsFPMath, "no-nans-fp-math"); + RESET_OPTION(NoSignedZerosFPMath, "no-signed-zeros-fp-math"); + RESET_OPTION(NoTrappingFPMath, "no-trapping-math"); + + StringRef Denormal = + F.getFnAttribute("denormal-fp-math").getValueAsString(); + if (Denormal == "ieee") + Options.FPDenormalMode = FPDenormal::IEEE; + else if (Denormal == "preserve-sign") + Options.FPDenormalMode = FPDenormal::PreserveSign; + else if (Denormal == "positive-zero") + Options.FPDenormalMode = FPDenormal::PositiveZero; + else + Options.FPDenormalMode = DefaultOptions.FPDenormalMode; +} + +/// Returns the code generation relocation model. The choices are static, PIC, +/// and dynamic-no-pic. +Reloc::Model TargetMachine::getRelocationModel() const { return RM; } + +/// Returns the code model. The choices are small, kernel, medium, large, and +/// target default. +CodeModel::Model TargetMachine::getCodeModel() const { return CMModel; } + +/// Get the IR-specified TLS model for Var. +static TLSModel::Model getSelectedTLSModel(const GlobalValue *GV) { + switch (GV->getThreadLocalMode()) { + case GlobalVariable::NotThreadLocal: + llvm_unreachable("getSelectedTLSModel for non-TLS variable"); + break; + case GlobalVariable::GeneralDynamicTLSModel: + return TLSModel::GeneralDynamic; + case GlobalVariable::LocalDynamicTLSModel: + return TLSModel::LocalDynamic; + case GlobalVariable::InitialExecTLSModel: + return TLSModel::InitialExec; + case GlobalVariable::LocalExecTLSModel: + return TLSModel::LocalExec; + } + llvm_unreachable("invalid TLS model"); +} + +bool TargetMachine::shouldAssumeDSOLocal(const Module &M, + const GlobalValue *GV) const { + Reloc::Model RM = getRelocationModel(); + const Triple &TT = getTargetTriple(); + + // DLLImport explicitly marks the GV as external. + if (GV && GV->hasDLLImportStorageClass()) + return false; + + // Every other GV is local on COFF. + // Make an exception for windows OS in the triple: Some firmwares builds use + // *-win32-macho triples. This (accidentally?) produced windows relocations + // without GOT tables in older clang versions; Keep this behaviour. + if (TT.isOSBinFormatCOFF() || (TT.isOSWindows() && TT.isOSBinFormatMachO())) + return true; + + if (GV && (GV->hasLocalLinkage() || !GV->hasDefaultVisibility())) + return true; + + if (TT.isOSBinFormatMachO()) { + if (RM == Reloc::Static) + return true; + return GV && GV->isStrongDefinitionForLinker(); + } + + assert(TT.isOSBinFormatELF()); + assert(RM != Reloc::DynamicNoPIC); + + bool IsExecutable = + RM == Reloc::Static || M.getPIELevel() != PIELevel::Default; + if (IsExecutable) { + // If the symbol is defined, it cannot be preempted. + if (GV && !GV->isDeclarationForLinker()) + return true; + + bool IsTLS = GV && GV->isThreadLocal(); + bool IsAccessViaCopyRelocs = Options.MCOptions.MCPIECopyRelocations && GV && + isa(GV) && + !GV->hasExternalWeakLinkage(); + Triple::ArchType Arch = TT.getArch(); + bool IsPPC = + Arch == Triple::ppc || Arch == Triple::ppc64 || Arch == Triple::ppc64le; + // Check if we can use copy relocations. PowerPC has no copy relocations. + if (!IsTLS && !IsPPC && (RM == Reloc::Static || IsAccessViaCopyRelocs)) + return true; + } + + // ELF supports preemption of other symbols. + return false; +} + +TLSModel::Model TargetMachine::getTLSModel(const GlobalValue *GV) const { + bool IsPIE = GV->getParent()->getPIELevel() != PIELevel::Default; + Reloc::Model RM = getRelocationModel(); + bool IsSharedLibrary = RM == Reloc::PIC_ && !IsPIE; + bool IsLocal = shouldAssumeDSOLocal(*GV->getParent(), GV); + + TLSModel::Model Model; + if (IsSharedLibrary) { + if (IsLocal) + Model = TLSModel::LocalDynamic; + else + Model = TLSModel::GeneralDynamic; + } else { + if (IsLocal) + Model = TLSModel::LocalExec; + else + Model = TLSModel::InitialExec; + } + + // If the user specified a more specific model, use that. + TLSModel::Model SelectedModel = getSelectedTLSModel(GV); + if (SelectedModel > Model) + return SelectedModel; + + return Model; +} + +/// Returns the optimization level: None, Less, Default, or Aggressive. +CodeGenOpt::Level TargetMachine::getOptLevel() const { return OptLevel; } + +void TargetMachine::setOptLevel(CodeGenOpt::Level Level) { OptLevel = Level; } + +TargetIRAnalysis TargetMachine::getTargetIRAnalysis() { + return TargetIRAnalysis([](const Function &F) { + return TargetTransformInfo(F.getParent()->getDataLayout()); + }); +} + +void TargetMachine::getNameWithPrefix(SmallVectorImpl &Name, + const GlobalValue *GV, Mangler &Mang, + bool MayAlwaysUsePrivate) const { + if (MayAlwaysUsePrivate || !GV->hasPrivateLinkage()) { + // Simple case: If GV is not private, it is not important to find out if + // private labels are legal in this case or not. + Mang.getNameWithPrefix(Name, GV, false); + return; + } + const TargetLoweringObjectFile *TLOF = getObjFileLowering(); + TLOF->getNameWithPrefix(Name, GV, *this); +} + +MCSymbol *TargetMachine::getSymbol(const GlobalValue *GV) const { + const TargetLoweringObjectFile *TLOF = getObjFileLowering(); + SmallString<128> NameStr; + getNameWithPrefix(NameStr, GV, TLOF->getMangler()); + return TLOF->getContext().getOrCreateSymbol(NameStr); +} diff --git a/llvm/lib/CodeGen/TargetMachineC.cpp b/llvm/lib/Target/TargetMachineC.cpp similarity index 100% rename from llvm/lib/CodeGen/TargetMachineC.cpp rename to llvm/lib/Target/TargetMachineC.cpp diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp index ad779c1b771e..8ad74d9db7b0 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp @@ -69,10 +69,11 @@ WebAssemblyTargetMachine::WebAssemblyTargetMachine( const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, CodeGenOpt::Level OL, bool JIT) - : TargetMachine(T, TT.isArch64Bit() ? "e-m:e-p:64:64-i64:64-n32:64-S128" - : "e-m:e-p:32:32-i64:64-n32:64-S128", - TT, CPU, FS, Options, getEffectiveRelocModel(RM), - CM ? *CM : CodeModel::Large, OL), + : LLVMTargetMachine(T, + TT.isArch64Bit() ? "e-m:e-p:64:64-i64:64-n32:64-S128" + : "e-m:e-p:32:32-i64:64-n32:64-S128", + TT, CPU, FS, Options, getEffectiveRelocModel(RM), + CM ? *CM : CodeModel::Large, OL), TLOF(TT.isOSBinFormatELF() ? static_cast( new WebAssemblyTargetObjectFileELF()) : diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h index 4bb7fb00f7b4..224849526514 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h @@ -21,7 +21,7 @@ namespace llvm { -class WebAssemblyTargetMachine final : public TargetMachine { +class WebAssemblyTargetMachine final : public LLVMTargetMachine { std::unique_ptr TLOF; mutable StringMap> SubtargetMap; diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp index b4ab8779672b..51ae377986d9 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.cpp +++ b/llvm/lib/Target/X86/X86TargetMachine.cpp @@ -200,7 +200,7 @@ X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT, Optional RM, Optional CM, CodeGenOpt::Level OL, bool JIT) - : TargetMachine( + : LLVMTargetMachine( T, computeDataLayout(TT), TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM), getEffectiveCodeModel(CM, JIT, TT.getArch() == Triple::x86_64), OL), diff --git a/llvm/lib/Target/X86/X86TargetMachine.h b/llvm/lib/Target/X86/X86TargetMachine.h index 25a51ffb4c12..952bd1321ff9 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.h +++ b/llvm/lib/Target/X86/X86TargetMachine.h @@ -28,7 +28,7 @@ class StringRef; class X86Subtarget; class X86RegisterBankInfo; -class X86TargetMachine final : public TargetMachine { +class X86TargetMachine final : public LLVMTargetMachine { std::unique_ptr TLOF; mutable StringMap> SubtargetMap; diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp index 2e932b95467f..3aa7187e0cd1 100644 --- a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp @@ -48,7 +48,7 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, const Triple &TT, Optional RM, Optional CM, CodeGenOpt::Level OL, bool JIT) - : TargetMachine( + : LLVMTargetMachine( T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32", TT, CPU, FS, Options, getEffectiveRelocModel(RM), getEffectiveCodeModel(CM), OL), diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.h b/llvm/lib/Target/XCore/XCoreTargetMachine.h index 8e6dde512e9d..5baa3524d2a6 100644 --- a/llvm/lib/Target/XCore/XCoreTargetMachine.h +++ b/llvm/lib/Target/XCore/XCoreTargetMachine.h @@ -24,7 +24,7 @@ namespace llvm { -class XCoreTargetMachine : public TargetMachine { +class XCoreTargetMachine : public LLVMTargetMachine { std::unique_ptr TLOF; XCoreSubtarget Subtarget; diff --git a/llvm/tools/llc/llc.cpp b/llvm/tools/llc/llc.cpp index 923095a00563..fe6b97e34b64 100644 --- a/llvm/tools/llc/llc.cpp +++ b/llvm/tools/llc/llc.cpp @@ -511,7 +511,8 @@ static int compileModule(char **argv, LLVMContext &Context) { } const char *argv0 = argv[0]; - MachineModuleInfo *MMI = new MachineModuleInfo(Target.get()); + LLVMTargetMachine &LLVMTM = static_cast(*Target); + MachineModuleInfo *MMI = new MachineModuleInfo(&LLVMTM); // Construct a custom pass pipeline that starts after instruction // selection. @@ -520,7 +521,7 @@ static int compileModule(char **argv, LLVMContext &Context) { errs() << argv0 << ": run-pass is for .mir file only.\n"; return 1; } - TargetPassConfig &TPC = *Target->createPassConfig(PM); + TargetPassConfig &TPC = *LLVMTM.createPassConfig(PM); if (TPC.hasLimitedCodeGenPipeline()) { errs() << argv0 << ": run-pass cannot be used with " << TPC.getLimitedCodeGenPipelineReason(" and ") << ".\n"; diff --git a/llvm/tools/opt/opt.cpp b/llvm/tools/opt/opt.cpp index a736107965c8..73f89c0e1555 100644 --- a/llvm/tools/opt/opt.cpp +++ b/llvm/tools/opt/opt.cpp @@ -593,9 +593,10 @@ int main(int argc, char **argv) { } if (TM) { - Pass *TPC = TM->createPassConfig(Passes); - if (TPC) - Passes.add(TPC); + // FIXME: We should dyn_cast this when supported. + auto <M = static_cast(*TM); + Pass *TPC = LTM.createPassConfig(Passes); + Passes.add(TPC); } // Create a new optimization pass for each one specified on the command line diff --git a/llvm/unittests/CodeGen/MachineInstrTest.cpp b/llvm/unittests/CodeGen/MachineInstrTest.cpp index bd61bf056ec6..89041e2ab22b 100644 --- a/llvm/unittests/CodeGen/MachineInstrTest.cpp +++ b/llvm/unittests/CodeGen/MachineInstrTest.cpp @@ -62,11 +62,11 @@ private: TargetInstrInfo TII; }; -class BogusTargetMachine : public TargetMachine { +class BogusTargetMachine : public LLVMTargetMachine { public: BogusTargetMachine() - : TargetMachine(Target(), "", Triple(""), "", "", TargetOptions(), - Reloc::Static, CodeModel::Small, CodeGenOpt::Default), + : LLVMTargetMachine(Target(), "", Triple(""), "", "", TargetOptions(), + Reloc::Static, CodeModel::Small, CodeGenOpt::Default), ST(*this) {} ~BogusTargetMachine() override {}