replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Fix PLD encoding. 

llvm-svn: 124458
This commit is contained in:
Evan Cheng 2011-01-27 23:48:34 +00:00
parent 59f5dc60d2
commit bb8420a070
2 changed files with 60 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -1107,14 +1107,13 @@ multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
let Inst{22} = read; let Inst{22} = read;
let Inst{21-20} = 0b01; let Inst{21-20} = 0b01;
let Inst{19-16} = addr{16-13}; // Rn let Inst{19-16} = addr{16-13}; // Rn
let Inst{15-12} = Rt; let Inst{15-12} = 0b1111;
let Inst{11-0} = addr{11-0}; // imm12 let Inst{11-0} = addr{11-0}; // imm12
} }
def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
!strconcat(opc, "\t$shift"), !strconcat(opc, "\t$shift"),
[(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> { [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
bits<4> Rt;
bits<17> shift; bits<17> shift;
let Inst{31-26} = 0b111101; let Inst{31-26} = 0b111101;
let Inst{25} = 1; // 1 for register form let Inst{25} = 1; // 1 for register form
@ -1123,6 +1122,7 @@ multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
let Inst{22} = read; let Inst{22} = read;
let Inst{21-20} = 0b01; let Inst{21-20} = 0b01;
let Inst{19-16} = shift{16-13}; // Rn let Inst{19-16} = shift{16-13}; // Rn
let Inst{15-12} = 0b1111;
let Inst{11-0} = shift{11-0}; let Inst{11-0} = shift{11-0};
} }
} }

58
llvm/test/MC/ARM/prefetch.ll Normal file
View File

@ -0,0 +1,58 @@
; RUN: llc < %s -march=arm -mattr=+v7a,+mp -show-mc-encoding | FileCheck %s -check-prefix=ARM
; RUN: llc < %s -march=thumb -mattr=+v7a -show-mc-encoding | FileCheck %s -check-prefix=T2
; rdar://8924681
define void @t1(i8* %ptr) nounwind {
entry:
; ARM: t1:
; ARM: pldw [r0] @ encoding: [0x00,0xf0,0x90,0xf5]
; ARM: pld [r0] @ encoding: [0x00,0xf0,0xd0,0xf5]
; T2: t1:
; T2: pld [r0] @ encoding: [0x90,0xf8,0x00,0xf0]
tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3 )
tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3 )
ret void
}
define void @t2(i8* %ptr) nounwind {
entry:
; ARM: t2:
; ARM: pld [r0, #1023] @ encoding: [0xff,0xf3,0xd0,0xf5]
; T2: t2:
; T2: pld [r0, #1023] @ encoding: [0x90,0xf8,0xff,0xf3]
%tmp = getelementptr i8* %ptr, i32 1023
tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3 )
ret void
}
define void @t3(i32 %base, i32 %offset) nounwind {
entry:
; ARM: t3:
; ARM: pld [r0, r1, lsr #2] @ encoding: [0x21,0xf1,0xd0,0xf7]
; T2: t3:
; T2: pld [r0, r1] @ encoding: [0x10,0xf8,0x01,0xf0]
%tmp1 = lshr i32 %offset, 2
%tmp2 = add i32 %base, %tmp1
%tmp3 = inttoptr i32 %tmp2 to i8*
tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3 )
ret void
}
define void @t4(i32 %base, i32 %offset) nounwind {
entry:
; ARM: t4:
; ARM: pld [r0, r1, lsl #2] @ encoding: [0x01,0xf1,0xd0,0xf7]
; T2: t4:
; T2: pld [r0, r1, lsl #2] @ encoding: [0x10,0xf8,0x21,0xf0]
%tmp1 = shl i32 %offset, 2
%tmp2 = add i32 %base, %tmp1
%tmp3 = inttoptr i32 %tmp2 to i8*
tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3 )
ret void
}
declare void @llvm.prefetch(i8*, i32, i32) nounwind