[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.
llvm-svn: 239935
This commit is contained in:
Colin LeMahieu
parent
35c1df5cb6
commit
bb71f7d251
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@ -0,0 +1,16 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: memub(r{{[0-9]+}}{{ *}}<<{{ *}}#1{{ *}}+{{ *}}##a)
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@a = external global [5 x [2 x i8]]
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define zeroext i8 @foo(i8 zeroext %l) nounwind readonly {
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for.end:
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%idxprom = zext i8 %l to i32
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%arrayidx1 = getelementptr inbounds [5 x [2 x i8]], [5 x [2 x i8]]* @a, i32 0, i32 %idxprom, i32 0
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%0 = load i8, i8* %arrayidx1, align 1
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%conv = zext i8 %0 to i32
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%mul = mul nsw i32 %conv, 20
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%conv2 = trunc i32 %mul to i8
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ret i8 %conv2
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}
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@ -0,0 +1,16 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: memuh(r{{[0-9]+}}{{ *}}<<{{ *}}#2{{ *}}+{{ *}}##a)
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@a = external global [5 x [2 x i16]]
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define signext i16 @foo(i16 zeroext %l) nounwind readonly {
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for.end:
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%idxprom = zext i16 %l to i32
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%arrayidx1 = getelementptr inbounds [5 x [2 x i16]], [5 x [2 x i16]]* @a, i32 0, i32 %idxprom, i32 0
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%0 = load i16, i16* %arrayidx1, align 2
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%conv = zext i16 %0 to i32
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%mul = mul nsw i32 %conv, 20
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%conv2 = trunc i32 %mul to i16
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ret i16 %conv2
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}
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@ -1,4 +1,4 @@
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; RUN: llc -march=hexagon -mcpu=hexagonv4 -O3 < %s | FileCheck %s
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; RUN: llc -march=hexagon -O3 < %s | FileCheck %s
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; CHECK-LABEL: @test_pos1_ir_slt
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; CHECK: loop0
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@ -1,4 +1,4 @@
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; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; Check that we generate a hardware loop instruction.
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; CHECK: endloop0
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@ -0,0 +1,43 @@
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; RUN: llc -march=hexagon -mcpu=hexagonv5 -hexagon-small-data-threshold=0 < %s | FileCheck %s
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target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32"
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target triple = "hexagon-unknown-linux-gnu"
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@flag = external global i1
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; CHECK-NOT: CONST
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define i32 @test_sextloadi1_32() {
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entry:
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%0 = load i1, i1* @flag, align 4
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%1 = sext i1 %0 to i32
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ret i32 %1
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}
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define i16 @test_zextloadi1_16() {
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entry:
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%0 = load i1, i1* @flag, align 4
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%1 = zext i1 %0 to i16
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ret i16 %1
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}
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define i32 @test_zextloadi1_32() {
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entry:
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%0 = load i1, i1* @flag, align 4
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%1 = zext i1 %0 to i32
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ret i32 %1
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}
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define i64 @test_zextloadi1_64() {
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entry:
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%0 = load i1, i1* @flag, align 4
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%1 = zext i1 %0 to i64
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ret i64 %1
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}
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@ -0,0 +1,43 @@
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; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s
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target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32"
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target triple = "hexagon-unknown-linux-gnu"
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@flag = external global i1
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; CHECK-NOT: CONST
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define i32 @test_sextloadi1_32() {
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entry:
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%0 = load i1, i1* @flag, align 4
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%1 = sext i1 %0 to i32
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ret i32 %1
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}
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define i16 @test_zextloadi1_16() {
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entry:
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%0 = load i1, i1* @flag, align 4
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%1 = zext i1 %0 to i16
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ret i16 %1
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}
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define i32 @test_zextloadi1_32() {
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entry:
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%0 = load i1, i1* @flag, align 4
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%1 = zext i1 %0 to i32
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ret i32 %1
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}
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define i64 @test_zextloadi1_64() {
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entry:
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%0 = load i1, i1* @flag, align 4
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%1 = zext i1 %0 to i64
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ret i64 %1
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}
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@ -0,0 +1,45 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32"
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target triple = "hexagon-unknown-linux-gnu"
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@flag = external global i1
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define i32 @test_sextloadi1_32() {
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entry:
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%0 = load i1, i1* @flag, align 4
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; CHECK: memub
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%1 = sext i1 %0 to i32
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ret i32 %1
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}
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define i16 @test_zextloadi1_16() {
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entry:
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%0 = load i1, i1* @flag, align 4
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; CHECK: memub
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%1 = zext i1 %0 to i16
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ret i16 %1
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}
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define i32 @test_zextloadi1_32() {
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entry:
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%0 = load i1, i1* @flag, align 4
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; CHECK: memub
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%1 = zext i1 %0 to i32
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ret i32 %1
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}
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define i64 @test_zextloadi1_64() {
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entry:
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%0 = load i1, i1* @flag, align 4
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; CHECK: memub
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%1 = zext i1 %0 to i64
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ret i64 %1
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}
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@ -0,0 +1,45 @@
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; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
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target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32"
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target triple = "hexagon-unknown-linux-gnu"
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@flag = external global i1
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define i32 @test_sextloadi1_32() {
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entry:
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%0 = load i1, i1* @flag, align 4
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; CHECK: memub
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%1 = sext i1 %0 to i32
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ret i32 %1
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}
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define i16 @test_zextloadi1_16() {
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entry:
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%0 = load i1, i1* @flag, align 4
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; CHECK: memub
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%1 = zext i1 %0 to i16
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ret i16 %1
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}
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define i32 @test_zextloadi1_32() {
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entry:
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%0 = load i1, i1* @flag, align 4
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; CHECK: memub
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%1 = zext i1 %0 to i32
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ret i32 %1
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}
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define i64 @test_zextloadi1_64() {
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entry:
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%0 = load i1, i1* @flag, align 4
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; CHECK: memub
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%1 = zext i1 %0 to i64
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ret i64 %1
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}
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@ -0,0 +1,9 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: max
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define i64 @f(i64 %src, i64 %maxval) nounwind readnone {
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entry:
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%cmp = icmp slt i64 %maxval, %src
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%cond = select i1 %cmp, i64 %src, i64 %maxval
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ret i64 %cond
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}
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@ -0,0 +1,23 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; The result of max(half-word, half-word) is also half-word.
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; Check that we are not producing a sign extend after the max.
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; CHECK-NOT: sxth
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define i64 @test_cast(i64 %arg0, i16 zeroext %arg1, i16 zeroext %arg2) nounwind readnone {
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entry:
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%conv.i = zext i16 %arg1 to i32
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%conv1.i = zext i16 %arg2 to i32
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%sub.i = sub nsw i32 %conv.i, %conv1.i
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%sext.i = shl i32 %sub.i, 16
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%cmp.i = icmp slt i32 %sext.i, 65536
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%0 = ashr exact i32 %sext.i, 16
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%conv7.i = select i1 %cmp.i, i32 1, i32 %0
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%cmp8.i = icmp sgt i32 %conv7.i, 4
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%conv7.op.i = add i32 %conv7.i, 65535
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%shl = shl i64 %arg0, 2
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%.mask = and i32 %conv7.op.i, 65535
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%1 = zext i32 %.mask to i64
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%conv = select i1 %cmp8.i, i64 3, i64 %1
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%or = or i64 %conv, %shl
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ret i64 %or
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}
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@ -0,0 +1,9 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: maxu
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define i64 @f(i64 %src, i64 %maxval) nounwind readnone {
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entry:
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%cmp = icmp ult i64 %maxval, %src
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%cond = select i1 %cmp, i64 %src, i64 %maxval
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ret i64 %cond
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}
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@ -0,0 +1,9 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: maxu
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define i32 @f(i32 %src, i32 %maxval) nounwind readnone {
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entry:
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%cmp = icmp ult i32 %maxval, %src
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%cond = select i1 %cmp, i32 %src, i32 %maxval
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ret i32 %cond
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}
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@ -0,0 +1,9 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: max
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define i32 @f(i32 %src, i32 %maxval) nounwind readnone {
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entry:
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%cmp = icmp slt i32 %maxval, %src
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%cond = select i1 %cmp, i32 %src, i32 %maxval
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ret i32 %cond
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}
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@ -0,0 +1,9 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: min
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define i64 @f(i64 %src, i64 %maxval) nounwind readnone {
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entry:
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%cmp = icmp sgt i64 %maxval, %src
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%cond = select i1 %cmp, i64 %src, i64 %maxval
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ret i64 %cond
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}
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@ -0,0 +1,11 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: minu
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define zeroext i16 @f(i16* noalias nocapture %src) nounwind readonly {
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entry:
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%arrayidx = getelementptr inbounds i16, i16* %src, i32 1
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%0 = load i16, i16* %arrayidx, align 1
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%cmp = icmp ult i16 %0, 32767
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%. = select i1 %cmp, i16 %0, i16 32767
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ret i16 %.
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}
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@ -0,0 +1,11 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: minu
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define zeroext i8 @f(i8* noalias nocapture %src) nounwind readonly {
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entry:
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%arrayidx = getelementptr inbounds i8, i8* %src, i32 1
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%0 = load i8, i8* %arrayidx, align 1
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%cmp = icmp ult i8 %0, 127
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%. = select i1 %cmp, i8 %0, i8 127
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ret i8 %.
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}
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@ -0,0 +1,9 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: minu
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define i64 @f(i64 %src, i64 %maxval) nounwind readnone {
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entry:
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%cmp = icmp ugt i64 %maxval, %src
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%cond = select i1 %cmp, i64 %src, i64 %maxval
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ret i64 %cond
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}
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@ -0,0 +1,9 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: minu
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define i32 @f(i32 %src, i32 %maxval) nounwind readnone {
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entry:
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%cmp = icmp ugt i32 %maxval, %src
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%cond = select i1 %cmp, i32 %src, i32 %maxval
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ret i32 %cond
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}
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@ -0,0 +1,9 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: min
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define i32 @f(i32 %src, i32 %maxval) nounwind readnone {
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entry:
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%cmp = icmp sgt i32 %maxval, %src
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%cond = select i1 %cmp, i32 %src, i32 %maxval
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ret i32 %cond
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}
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