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Change TargetLowering::RegisterTypeForVT to contain MVTs, instead of 

EVTs.

llvm-svn: 170535
This commit is contained in:
Patrik Hagglund 2012-12-19 11:48:16 +00:00
parent 93060569ba
commit bad545ccba
7 changed files with 24 additions and 24 deletions
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8
llvm/include/llvm/Target/TargetLowering.h
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@ -585,14 +585,14 @@ public:
/// getRegisterType - Return the type of registers that this ValueType will /// getRegisterType - Return the type of registers that this ValueType will
/// eventually require. /// eventually require.
EVT getRegisterType(MVT VT) const { MVT getRegisterType(MVT VT) const {
assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)); assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
return RegisterTypeForVT[VT.SimpleTy]; return RegisterTypeForVT[VT.SimpleTy];
} }
/// getRegisterType - Return the type of registers that this ValueType will /// getRegisterType - Return the type of registers that this ValueType will
/// eventually require. /// eventually require.
EVT getRegisterType(LLVMContext &Context, EVT VT) const { MVT getRegisterType(LLVMContext &Context, EVT VT) const {
if (VT.isSimple()) { if (VT.isSimple()) {
assert((unsigned)VT.getSimpleVT().SimpleTy < assert((unsigned)VT.getSimpleVT().SimpleTy <
array_lengthof(RegisterTypeForVT)); array_lengthof(RegisterTypeForVT));
@ -603,7 +603,7 @@ public:
unsigned NumIntermediates; unsigned NumIntermediates;
(void)getVectorTypeBreakdown(Context, VT, VT1, (void)getVectorTypeBreakdown(Context, VT, VT1,
NumIntermediates, RegisterVT); NumIntermediates, RegisterVT);
return RegisterVT; return RegisterVT.getSimpleVT();
} }
if (VT.isInteger()) { if (VT.isInteger()) {
return getRegisterType(Context, getTypeToTransformTo(Context, VT)); return getRegisterType(Context, getTypeToTransformTo(Context, VT));
@ -1931,7 +1931,7 @@ private:
/// each ValueType the target supports natively. /// each ValueType the target supports natively.
const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
EVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
/// RepRegClassForVT - This indicates the "representative" register class to /// RepRegClassForVT - This indicates the "representative" register class to
/// use for each ValueType the target supports natively. This information is /// use for each ValueType the target supports natively. This information is

2
llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
View File

@ -226,7 +226,7 @@ unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
unsigned FirstReg = 0; unsigned FirstReg = 0;
for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
EVT ValueVT = ValueVTs[Value]; EVT ValueVT = ValueVTs[Value];
MVT RegisterVT = TLI.getRegisterType(Ty->getContext(), ValueVT).getSimpleVT(); MVT RegisterVT = TLI.getRegisterType(Ty->getContext(), ValueVT);
unsigned NumRegs = TLI.getNumRegisters(Ty->getContext(), ValueVT); unsigned NumRegs = TLI.getNumRegisters(Ty->getContext(), ValueVT);
for (unsigned i = 0; i != NumRegs; ++i) { for (unsigned i = 0; i != NumRegs; ++i) {

4
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -321,7 +321,7 @@ static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
// Do a (aligned) store to a stack slot, then copy from the stack slot // Do a (aligned) store to a stack slot, then copy from the stack slot
// to the final destination using (unaligned) integer loads and stores. // to the final destination using (unaligned) integer loads and stores.
EVT StoredVT = ST->getMemoryVT(); EVT StoredVT = ST->getMemoryVT();
EVT RegVT = MVT RegVT =
TLI.getRegisterType(*DAG.getContext(), TLI.getRegisterType(*DAG.getContext(),
EVT::getIntegerVT(*DAG.getContext(), EVT::getIntegerVT(*DAG.getContext(),
StoredVT.getSizeInBits())); StoredVT.getSizeInBits()));
@ -447,7 +447,7 @@ ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
// Copy the value to a (aligned) stack slot using (unaligned) integer // Copy the value to a (aligned) stack slot using (unaligned) integer
// loads and stores, then do a (aligned) load from the stack slot. // loads and stores, then do a (aligned) load from the stack slot.
EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
unsigned RegBytes = RegVT.getSizeInBits() / 8; unsigned RegBytes = RegVT.getSizeInBits() / 8;
unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;

2
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -703,7 +703,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc(); DebugLoc dl = N->getDebugLoc();
EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT); unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
// The argument is passed as NumRegs registers of type RegVT. // The argument is passed as NumRegs registers of type RegVT.

20
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -610,7 +610,7 @@ namespace {
for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
EVT ValueVT = ValueVTs[Value]; EVT ValueVT = ValueVTs[Value];
unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
EVT RegisterVT = tli.getRegisterType(Context, ValueVT); MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
for (unsigned i = 0; i != NumRegs; ++i) for (unsigned i = 0; i != NumRegs; ++i)
Regs.push_back(Reg + i); Regs.push_back(Reg + i);
RegVTs.push_back(RegisterVT); RegVTs.push_back(RegisterVT);
@ -1238,7 +1238,7 @@ void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind); VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind);
unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); MVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
SmallVector<SDValue, 4> Parts(NumParts); SmallVector<SDValue, 4> Parts(NumParts);
getCopyToParts(DAG, getCurDebugLoc(), getCopyToParts(DAG, getCurDebugLoc(),
SDValue(RetOp.getNode(), RetOp.getResNo() + j), SDValue(RetOp.getNode(), RetOp.getResNo() + j),
@ -6412,7 +6412,7 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
Flags.setNest(); Flags.setNest();
Flags.setOrigAlign(OriginalAlignment); Flags.setOrigAlign(OriginalAlignment);
EVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT); MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT); unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
SmallVector<SDValue, 4> Parts(NumParts); SmallVector<SDValue, 4> Parts(NumParts);
ISD::NodeType ExtendKind = ISD::ANY_EXTEND; ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
@ -6447,11 +6447,11 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
ComputeValueVTs(*this, CLI.RetTy, RetTys); ComputeValueVTs(*this, CLI.RetTy, RetTys);
for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
EVT VT = RetTys[I]; EVT VT = RetTys[I];
EVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT); MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
for (unsigned i = 0; i != NumRegs; ++i) { for (unsigned i = 0; i != NumRegs; ++i) {
ISD::InputArg MyFlags; ISD::InputArg MyFlags;
MyFlags.VT = RegisterVT.getSimpleVT(); MyFlags.VT = RegisterVT;
MyFlags.Used = CLI.IsReturnValueUsed; MyFlags.Used = CLI.IsReturnValueUsed;
if (CLI.RetSExt) if (CLI.RetSExt)
MyFlags.Flags.setSExt(); MyFlags.Flags.setSExt();
@ -6501,7 +6501,7 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
unsigned CurReg = 0; unsigned CurReg = 0;
for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
EVT VT = RetTys[I]; EVT VT = RetTys[I];
EVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT); MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg], ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
@ -6591,7 +6591,7 @@ void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
// or one register. // or one register.
ISD::ArgFlagsTy Flags; ISD::ArgFlagsTy Flags;
Flags.setSRet(); Flags.setSRet();
EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); MVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
ISD::InputArg RetArg(Flags, RegisterVT, true, 0, 0); ISD::InputArg RetArg(Flags, RegisterVT, true, 0, 0);
Ins.push_back(RetArg); Ins.push_back(RetArg);
} }
@ -6637,7 +6637,7 @@ void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
Flags.setNest(); Flags.setNest();
Flags.setOrigAlign(OriginalAlignment); Flags.setOrigAlign(OriginalAlignment);
EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); MVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
for (unsigned i = 0; i != NumRegs; ++i) { for (unsigned i = 0; i != NumRegs; ++i) {
ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed, ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed,
@ -6684,7 +6684,7 @@ void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
SmallVector<EVT, 1> ValueVTs; SmallVector<EVT, 1> ValueVTs;
ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
MVT VT = ValueVTs[0].getSimpleVT(); MVT VT = ValueVTs[0].getSimpleVT();
MVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT).getSimpleVT(); MVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
ISD::NodeType AssertOp = ISD::DELETED_NODE; ISD::NodeType AssertOp = ISD::DELETED_NODE;
SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
RegVT, VT, NULL, AssertOp); RegVT, VT, NULL, AssertOp);
@ -6716,7 +6716,7 @@ void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
for (unsigned Val = 0; Val != NumValues; ++Val) { for (unsigned Val = 0; Val != NumValues; ++Val) {
EVT VT = ValueVTs[Val]; EVT VT = ValueVTs[Val];
EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); MVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
if (!I->use_empty()) { if (!I->use_empty()) {

8
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -688,7 +688,7 @@ static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
if (!isPowerOf2_32(NewVTSize)) if (!isPowerOf2_32(NewVTSize))
NewVTSize = NextPowerOf2(NewVTSize); NewVTSize = NextPowerOf2(NewVTSize);
EVT DestVT = TLI->getRegisterType(NewVT); MVT DestVT = TLI->getRegisterType(NewVT);
RegisterVT = DestVT; RegisterVT = DestVT;
if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
@ -870,7 +870,7 @@ void TargetLowering::computeRegisterProperties() {
NumRegistersForVT[i] = NumRegistersForVT[i] =
getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
RegisterVT, this); RegisterVT, this);
RegisterTypeForVT[i] = RegisterVT; RegisterTypeForVT[i] = RegisterVT.getSimpleVT();
MVT NVT = VT.getPow2VectorType(); MVT NVT = VT.getPow2VectorType();
if (NVT == VT) { if (NVT == VT) {
@ -1011,13 +1011,13 @@ void llvm::GetReturnInfo(Type* ReturnType, Attribute attr,
// conventions. The frontend should mark functions whose return values // conventions. The frontend should mark functions whose return values
// require promoting with signext or zeroext attributes. // require promoting with signext or zeroext attributes.
if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
if (VT.bitsLT(MinVT)) if (VT.bitsLT(MinVT))
VT = MinVT; VT = MinVT;
} }
unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
// 'inreg' on function refers to return value // 'inreg' on function refers to return value
ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();

4
llvm/lib/Target/X86/X86FastISel.cpp
View File

@ -1909,11 +1909,11 @@ bool X86FastISel::DoSelectCall(const Instruction *I, const char *MemIntName) {
ComputeValueVTs(TLI, I->getType(), RetTys); ComputeValueVTs(TLI, I->getType(), RetTys);
for (unsigned i = 0, e = RetTys.size(); i != e; ++i) { for (unsigned i = 0, e = RetTys.size(); i != e; ++i) {
EVT VT = RetTys[i]; EVT VT = RetTys[i];
EVT RegisterVT = TLI.getRegisterType(I->getParent()->getContext(), VT); MVT RegisterVT = TLI.getRegisterType(I->getParent()->getContext(), VT);
unsigned NumRegs = TLI.getNumRegisters(I->getParent()->getContext(), VT); unsigned NumRegs = TLI.getNumRegisters(I->getParent()->getContext(), VT);
for (unsigned j = 0; j != NumRegs; ++j) { for (unsigned j = 0; j != NumRegs; ++j) {
ISD::InputArg MyFlags; ISD::InputArg MyFlags;
MyFlags.VT = RegisterVT.getSimpleVT(); MyFlags.VT = RegisterVT;
MyFlags.Used = !CS.getInstruction()->use_empty(); MyFlags.Used = !CS.getInstruction()->use_empty();
if (CS.paramHasAttr(0, Attribute::SExt)) if (CS.paramHasAttr(0, Attribute::SExt))
MyFlags.Flags.setSExt(); MyFlags.Flags.setSExt();