[X86] Adding support for missing variations of X86 string related instructions
The following are legal according to X86 spec: ins mem, DX outs DX, mem lods mem stos mem scas mem cmps mem, mem movs mem, mem Differential Revision: http://reviews.llvm.org/D14827 llvm-svn: 258132
This commit is contained in:
Marina Yatsina
parent
b5d539380a
commit
b9f4f62cfe
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@ -683,9 +683,14 @@ private:
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std::unique_ptr<X86Operand> DefaultMemSIOperand(SMLoc Loc);
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std::unique_ptr<X86Operand> DefaultMemDIOperand(SMLoc Loc);
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void AddDefaultSrcDestOperands(
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OperandVector& Operands, std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
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std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst);
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bool IsSIReg(unsigned Reg);
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unsigned GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, bool IsSIReg);
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void
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AddDefaultSrcDestOperands(OperandVector &Operands,
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std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
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std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst);
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bool VerifyAndAdjustOperands(OperandVector &OrigOperands,
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OperandVector &FinalOperands);
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std::unique_ptr<X86Operand> ParseOperand();
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std::unique_ptr<X86Operand> ParseATTOperand();
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std::unique_ptr<X86Operand> ParseIntelOperand();
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@ -747,11 +752,6 @@ private:
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bool OmitRegisterFromClobberLists(unsigned RegNo) override;
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/// doSrcDstMatch - Returns true if operands are matching in their
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/// word size (%si and %di, %esi and %edi, etc.). Order depends on
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/// the parsing mode (Intel vs. AT&T).
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bool doSrcDstMatch(X86Operand &Op1, X86Operand &Op2);
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/// Parses AVX512 specific operand primitives: masked registers ({%k<NUM>}, {z})
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/// and memory broadcasting ({1to<NUM>}) primitives, updating Operands vector if required.
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/// \return \c true if no parsing errors occurred, \c false otherwise.
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@ -867,27 +867,6 @@ static bool CheckBaseRegAndIndexReg(unsigned BaseReg, unsigned IndexReg,
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return false;
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}
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bool X86AsmParser::doSrcDstMatch(X86Operand &Op1, X86Operand &Op2)
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{
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// Return true and let a normal complaint about bogus operands happen.
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if (!Op1.isMem() || !Op2.isMem())
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return true;
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// Actually these might be the other way round if Intel syntax is
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// being used. It doesn't matter.
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unsigned diReg = Op1.Mem.BaseReg;
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unsigned siReg = Op2.Mem.BaseReg;
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if (X86MCRegisterClasses[X86::GR16RegClassID].contains(siReg))
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return X86MCRegisterClasses[X86::GR16RegClassID].contains(diReg);
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if (X86MCRegisterClasses[X86::GR32RegClassID].contains(siReg))
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return X86MCRegisterClasses[X86::GR32RegClassID].contains(diReg);
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if (X86MCRegisterClasses[X86::GR64RegClassID].contains(siReg))
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return X86MCRegisterClasses[X86::GR64RegClassID].contains(diReg);
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// Again, return true and let another error happen.
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return true;
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}
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bool X86AsmParser::ParseRegister(unsigned &RegNo,
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SMLoc &StartLoc, SMLoc &EndLoc) {
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MCAsmParser &Parser = getParser();
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@ -1025,6 +1004,37 @@ std::unique_ptr<X86Operand> X86AsmParser::DefaultMemDIOperand(SMLoc Loc) {
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Loc, Loc, 0);
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}
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bool X86AsmParser::IsSIReg(unsigned Reg) {
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switch (Reg) {
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default:
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assert("Only (R|E)SI and (R|E)DI are expected!");
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return false;
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case X86::RSI:
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case X86::ESI:
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case X86::SI:
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return true;
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case X86::RDI:
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case X86::EDI:
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case X86::DI:
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return false;
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}
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}
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unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg,
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bool IsSIReg) {
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switch (RegClassID) {
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default:
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assert("Unexpected register class");
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return Reg;
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case X86::GR64RegClassID:
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return IsSIReg ? X86::RSI : X86::RDI;
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case X86::GR32RegClassID:
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return IsSIReg ? X86::ESI : X86::EDI;
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case X86::GR16RegClassID:
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return IsSIReg ? X86::SI : X86::DI;
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}
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}
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void X86AsmParser::AddDefaultSrcDestOperands(
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OperandVector& Operands, std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
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std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst) {
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@ -1038,6 +1048,76 @@ void X86AsmParser::AddDefaultSrcDestOperands(
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}
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}
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bool X86AsmParser::VerifyAndAdjustOperands(OperandVector &OrigOperands,
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OperandVector &FinalOperands) {
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if (OrigOperands.size() > 1) {
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// Check if sizes match, OrigOpernads also contains the instruction name
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assert(OrigOperands.size() == FinalOperands.size() + 1 &&
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"Opernand size mismatch");
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// Verify types match
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int RegClassID = -1;
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for (unsigned int i = 0; i < FinalOperands.size(); ++i) {
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X86Operand &OrigOp = static_cast<X86Operand &>(*OrigOperands[i + 1]);
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X86Operand &FinalOp = static_cast<X86Operand &>(*FinalOperands[i]);
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if (FinalOp.isReg() &&
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(!OrigOp.isReg() || FinalOp.getReg() != OrigOp.getReg()))
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// Return false and let a normal complaint about bogus operands happen
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return false;
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if (FinalOp.isMem()) {
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if (!OrigOp.isMem())
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// Return false and let a normal complaint about bogus operands happen
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return false;
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unsigned OrigReg = OrigOp.Mem.BaseReg;
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unsigned FinalReg = FinalOp.Mem.BaseReg;
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// If we've already encounterd a register class, make sure all register
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// bases are of the same register class
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if (RegClassID != -1 &&
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!X86MCRegisterClasses[RegClassID].contains(OrigReg)) {
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return Error(OrigOp.getStartLoc(),
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"mismatching source and destination index registers");
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}
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if (X86MCRegisterClasses[X86::GR64RegClassID].contains(OrigReg))
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RegClassID = X86::GR64RegClassID;
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else if (X86MCRegisterClasses[X86::GR32RegClassID].contains(OrigReg))
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RegClassID = X86::GR32RegClassID;
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else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg))
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RegClassID = X86::GR16RegClassID;
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bool IsSI = IsSIReg(FinalReg);
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FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI);
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if (FinalReg != OrigReg) {
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std::string RegName = IsSI ? "ES:(R|E)SI" : "ES:(R|E)DI";
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Warning(OrigOp.getStartLoc(),
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"memory operand is only for determining the size, " +
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RegName + " will be used for the location");
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}
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FinalOp.Mem.Size = OrigOp.Mem.Size;
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FinalOp.Mem.SegReg = OrigOp.Mem.SegReg;
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FinalOp.Mem.BaseReg = FinalReg;
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}
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}
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// Remove old operandss
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for (unsigned int i = 0; i < FinalOperands.size(); ++i)
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OrigOperands.pop_back();
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}
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// OrigOperands.append(FinalOperands.begin(), FinalOperands.end());
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for (unsigned int i = 0; i < FinalOperands.size(); ++i)
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OrigOperands.push_back(std::move(FinalOperands[i]));
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return false;
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}
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std::unique_ptr<X86Operand> X86AsmParser::ParseOperand() {
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if (isParsingIntelSyntax())
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return ParseIntelOperand();
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@ -2274,84 +2354,92 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
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}
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}
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SmallVector<std::unique_ptr<MCParsedAsmOperand>, 2> TmpOperands;
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bool HadVerifyError = false;
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// Append default arguments to "ins[bwld]"
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if (Name.startswith("ins") && Operands.size() == 1 &&
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(Name == "insb" || Name == "insw" || Name == "insl" || Name == "insd")) {
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AddDefaultSrcDestOperands(Operands,
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if (Name.startswith("ins") &&
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(Operands.size() == 1 || Operands.size() == 3) &&
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(Name == "insb" || Name == "insw" || Name == "insl" || Name == "insd" ||
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Name == "ins")) {
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AddDefaultSrcDestOperands(TmpOperands,
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X86Operand::CreateReg(X86::DX, NameLoc, NameLoc),
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DefaultMemDIOperand(NameLoc));
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HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
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}
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// Append default arguments to "outs[bwld]"
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if (Name.startswith("outs") && Operands.size() == 1 &&
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if (Name.startswith("outs") &&
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(Operands.size() == 1 || Operands.size() == 3) &&
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(Name == "outsb" || Name == "outsw" || Name == "outsl" ||
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Name == "outsd" )) {
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AddDefaultSrcDestOperands(Operands,
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DefaultMemSIOperand(NameLoc),
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Name == "outsd" || Name == "outs")) {
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AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc),
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X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
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HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
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}
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// Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate
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// values of $SIREG according to the mode. It would be nice if this
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// could be achieved with InstAlias in the tables.
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if (Name.startswith("lods") && Operands.size() == 1 &&
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if (Name.startswith("lods") &&
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(Operands.size() == 1 || Operands.size() == 2) &&
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(Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
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Name == "lodsl" || Name == "lodsd" || Name == "lodsq"))
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Operands.push_back(DefaultMemSIOperand(NameLoc));
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Name == "lodsl" || Name == "lodsd" || Name == "lodsq")) {
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TmpOperands.push_back(DefaultMemSIOperand(NameLoc));
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HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
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}
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// Transform "stos[bwlq]" into "stos[bwlq] ($DIREG)" for appropriate
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// values of $DIREG according to the mode. It would be nice if this
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// could be achieved with InstAlias in the tables.
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if (Name.startswith("stos") && Operands.size() == 1 &&
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if (Name.startswith("stos") &&
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(Operands.size() == 1 || Operands.size() == 2) &&
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(Name == "stos" || Name == "stosb" || Name == "stosw" ||
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Name == "stosl" || Name == "stosd" || Name == "stosq"))
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Operands.push_back(DefaultMemDIOperand(NameLoc));
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Name == "stosl" || Name == "stosd" || Name == "stosq")) {
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TmpOperands.push_back(DefaultMemDIOperand(NameLoc));
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HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
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}
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// Transform "scas[bwlq]" into "scas[bwlq] ($DIREG)" for appropriate
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// values of $DIREG according to the mode. It would be nice if this
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// could be achieved with InstAlias in the tables.
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if (Name.startswith("scas") && Operands.size() == 1 &&
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if (Name.startswith("scas") &&
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(Operands.size() == 1 || Operands.size() == 2) &&
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(Name == "scas" || Name == "scasb" || Name == "scasw" ||
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Name == "scasl" || Name == "scasd" || Name == "scasq"))
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Operands.push_back(DefaultMemDIOperand(NameLoc));
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Name == "scasl" || Name == "scasd" || Name == "scasq")) {
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TmpOperands.push_back(DefaultMemDIOperand(NameLoc));
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HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
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}
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// Add default SI and DI operands to "cmps[bwlq]".
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if (Name.startswith("cmps") &&
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(Operands.size() == 1 || Operands.size() == 3) &&
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(Name == "cmps" || Name == "cmpsb" || Name == "cmpsw" ||
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Name == "cmpsl" || Name == "cmpsd" || Name == "cmpsq")) {
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if (Operands.size() == 1) {
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AddDefaultSrcDestOperands(Operands,
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DefaultMemDIOperand(NameLoc),
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DefaultMemSIOperand(NameLoc));
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} else if (Operands.size() == 3) {
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X86Operand &Op = (X86Operand &)*Operands[1];
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X86Operand &Op2 = (X86Operand &)*Operands[2];
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if (!doSrcDstMatch(Op, Op2))
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return Error(Op.getStartLoc(),
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"mismatching source and destination index registers");
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}
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AddDefaultSrcDestOperands(TmpOperands, DefaultMemDIOperand(NameLoc),
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DefaultMemSIOperand(NameLoc));
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HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
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}
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// Add default SI and DI operands to "movs[bwlq]".
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if ((Name.startswith("movs") &&
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(Name == "movs" || Name == "movsb" || Name == "movsw" ||
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Name == "movsl" || Name == "movsd" || Name == "movsq")) ||
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(Name.startswith("smov") &&
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(Name == "smov" || Name == "smovb" || Name == "smovw" ||
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Name == "smovl" || Name == "smovd" || Name == "smovq"))) {
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if (Operands.size() == 1) {
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if (Name == "movsd")
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Operands.back() = X86Operand::CreateToken("movsl", NameLoc);
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AddDefaultSrcDestOperands(Operands,
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DefaultMemSIOperand(NameLoc),
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DefaultMemDIOperand(NameLoc));
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} else if (Operands.size() == 3) {
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X86Operand &Op = (X86Operand &)*Operands[1];
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X86Operand &Op2 = (X86Operand &)*Operands[2];
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if (!doSrcDstMatch(Op, Op2))
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return Error(Op.getStartLoc(),
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"mismatching source and destination index registers");
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}
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if (((Name.startswith("movs") &&
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(Name == "movs" || Name == "movsb" || Name == "movsw" ||
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Name == "movsl" || Name == "movsd" || Name == "movsq")) ||
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(Name.startswith("smov") &&
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(Name == "smov" || Name == "smovb" || Name == "smovw" ||
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Name == "smovl" || Name == "smovd" || Name == "smovq"))) &&
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(Operands.size() == 1 || Operands.size() == 3)) {
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if (Name == "movsd" && Operands.size() == 1)
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Operands.back() = X86Operand::CreateToken("movsl", NameLoc);
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AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc),
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DefaultMemDIOperand(NameLoc));
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HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
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}
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// Check if we encountered an error for one the string insturctions
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if (HadVerifyError) {
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return HadVerifyError;
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}
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// FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
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@ -2782,6 +2782,11 @@ def : InstAlias<"lods\t{$src, %al|al, $src}", (LODSB srcidx8:$src), 0>;
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def : InstAlias<"lods\t{$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>;
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def : InstAlias<"lods\t{$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>;
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def : InstAlias<"lods\t{$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
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def : InstAlias<"lods\t$src", (LODSB srcidx8:$src), 0>;
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def : InstAlias<"lods\t$src", (LODSW srcidx16:$src), 0>;
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def : InstAlias<"lods\t$src", (LODSL srcidx32:$src), 0>;
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def : InstAlias<"lods\t$src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
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// stos aliases. Accept the source being omitted because it's implicit in
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// the mnemonic, or the mnemonic suffix being omitted because it's implicit
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@ -2794,6 +2799,11 @@ def : InstAlias<"stos\t{%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>;
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def : InstAlias<"stos\t{%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>;
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def : InstAlias<"stos\t{%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>;
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def : InstAlias<"stos\t{%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
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def : InstAlias<"stos\t$dst", (STOSB dstidx8:$dst), 0>;
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def : InstAlias<"stos\t$dst", (STOSW dstidx16:$dst), 0>;
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def : InstAlias<"stos\t$dst", (STOSL dstidx32:$dst), 0>;
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def : InstAlias<"stos\t$dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
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// scas aliases. Accept the destination being omitted because it's implicit
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// in the mnemonic, or the mnemonic suffix being omitted because it's implicit
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@ -2806,6 +2816,24 @@ def : InstAlias<"scas\t{$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>;
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def : InstAlias<"scas\t{$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>;
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def : InstAlias<"scas\t{$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>;
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def : InstAlias<"scas\t{$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
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def : InstAlias<"scas\t$dst", (SCASB dstidx8:$dst), 0>;
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def : InstAlias<"scas\t$dst", (SCASW dstidx16:$dst), 0>;
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def : InstAlias<"scas\t$dst", (SCASL dstidx32:$dst), 0>;
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def : InstAlias<"scas\t$dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
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// cmps aliases. Mnemonic suffix being omitted because it's implicit
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// in the destination.
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def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSB dstidx8:$dst, srcidx8:$src), 0>;
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def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSW dstidx16:$dst, srcidx16:$src), 0>;
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def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSL dstidx32:$dst, srcidx32:$src), 0>;
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def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSQ dstidx64:$dst, srcidx64:$src), 0>, Requires<[In64BitMode]>;
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// movs aliases. Mnemonic suffix being omitted because it's implicit
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||||
// in the destination.
|
||||
def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSB dstidx8:$dst, srcidx8:$src), 0>;
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||||
def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSW dstidx16:$dst, srcidx16:$src), 0>;
|
||||
def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSL dstidx32:$dst, srcidx32:$src), 0>;
|
||||
def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSQ dstidx64:$dst, srcidx64:$src), 0>, Requires<[In64BitMode]>;
|
||||
|
||||
// div and idiv aliases for explicit A register.
|
||||
def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
|
||||
|
|
@ -2918,6 +2946,18 @@ def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i3
|
|||
def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>;
|
||||
def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>;
|
||||
|
||||
// ins aliases. Accept the mnemonic suffix being omitted because it's implicit
|
||||
// in the destination.
|
||||
def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSB dstidx8:$dst), 0>;
|
||||
def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSW dstidx16:$dst), 0>;
|
||||
def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSL dstidx32:$dst), 0>;
|
||||
|
||||
// outs aliases. Accept the mnemonic suffix being omitted because it's implicit
|
||||
// in the source.
|
||||
def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSB srcidx8:$src), 0>;
|
||||
def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSW srcidx16:$src), 0>;
|
||||
def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSL srcidx32:$src), 0>;
|
||||
|
||||
// inb %dx -> inb %al, %dx
|
||||
def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
|
||||
def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
|
||||
|
|
|
|||
|
|
@ -144,3 +144,19 @@ insw %dx, (%edi)
|
|||
// 64: insw %dx, %es:(%edi) # encoding: [0x66,0x67,0x6d]
|
||||
// 32: insw %dx, %es:(%edi) # encoding: [0x66,0x6d]
|
||||
// 16: insw %dx, %es:(%edi) # encoding: [0x67,0x6d]
|
||||
|
||||
insw %dx, (%bx)
|
||||
// ERR64: invalid 16-bit base register
|
||||
// 32: insw %dx, %es:(%di) # encoding: [0x66,0x67,0x6d]
|
||||
// 16: insw %dx, %es:(%di) # encoding: [0x6d]
|
||||
|
||||
insw %dx, (%ebx)
|
||||
// 64: insw %dx, %es:(%edi) # encoding: [0x66,0x67,0x6d]
|
||||
// 32: insw %dx, %es:(%edi) # encoding: [0x66,0x6d]
|
||||
// 16: insw %dx, %es:(%edi) # encoding: [0x67,0x6d]
|
||||
|
||||
insw %dx, (%rbx)
|
||||
// 64: insw %dx, %es:(%rdi) # encoding: [0x66,0x6d]
|
||||
// ERR32: 64-bit
|
||||
// ERR16: 64-bit
|
||||
|
||||
|
|
|
|||
|
|
@ -751,3 +751,27 @@ loopnz _foo
|
|||
|
||||
sidt fword ptr [eax]
|
||||
// CHECK: sidtq (%eax)
|
||||
|
||||
ins byte ptr [eax], dx
|
||||
// CHECK: insb %dx, %es:(%edi)
|
||||
// CHECK-STDERR: memory operand is only for determining the size, ES:(R|E)DI will be used for the location
|
||||
outs dx, word ptr [eax]
|
||||
// CHECK: outsw (%esi), %dx
|
||||
// CHECK-STDERR: memory operand is only for determining the size, ES:(R|E)SI will be used for the location
|
||||
lods dword ptr [eax]
|
||||
// CHECK: lodsl (%esi), %eax
|
||||
// CHECK-STDERR: memory operand is only for determining the size, ES:(R|E)SI will be used for the location
|
||||
stos qword ptr [eax]
|
||||
// CHECK: stosq %rax, %es:(%edi)
|
||||
// CHECK-STDERR: memory operand is only for determining the size, ES:(R|E)DI will be used for the location
|
||||
scas byte ptr [eax]
|
||||
// CHECK: scasb %es:(%edi), %al
|
||||
// CHECK-STDERR: memory operand is only for determining the size, ES:(R|E)DI will be used for the location
|
||||
cmps word ptr [eax], word ptr [ebx]
|
||||
// CHECK: cmpsw %es:(%edi), (%esi)
|
||||
// CHECK-STDERR: memory operand is only for determining the size, ES:(R|E)SI will be used for the location
|
||||
// CHECK-STDERR: memory operand is only for determining the size, ES:(R|E)DI will be used for the location
|
||||
movs dword ptr [eax], dword ptr [ebx]
|
||||
// CHECK: movsl (%esi), %es:(%edi)
|
||||
// CHECK-STDERR: memory operand is only for determining the size, ES:(R|E)DI will be used for the location
|
||||
// CHECK-STDERR: memory operand is only for determining the size, ES:(R|E)SI will be used for the location
|
||||
|
|
|
|||
Loading…
Reference in New Issue