[AArch64] Cleanup of HasFullFP16 argument. NFC.
This is a clean up of commit r311154; it's not necessary to pass HasFullFP16 as an argument, instead just query the DAG. Differential Revision: https://reviews.llvm.org/D36978 llvm-svn: 311438
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@ -1440,9 +1440,10 @@ static bool isLegalArithImmed(uint64_t C) {
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}
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static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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const SDLoc &dl, SelectionDAG &DAG,
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bool FullFP16 = false) {
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const SDLoc &dl, SelectionDAG &DAG) {
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EVT VT = LHS.getValueType();
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const bool FullFP16 =
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static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasFullFP16();
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if (VT.isFloatingPoint()) {
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assert(VT != MVT::f128);
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@ -1534,9 +1535,11 @@ static SDValue emitConditionalComparison(SDValue LHS, SDValue RHS,
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ISD::CondCode CC, SDValue CCOp,
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AArch64CC::CondCode Predicate,
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AArch64CC::CondCode OutCC,
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const SDLoc &DL, SelectionDAG &DAG,
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bool FullFP16 = false) {
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const SDLoc &DL, SelectionDAG &DAG) {
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unsigned Opcode = 0;
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const bool FullFP16 =
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static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasFullFP16();
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if (LHS.getValueType().isFloatingPoint()) {
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assert(LHS.getValueType() != MVT::f128);
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if (LHS.getValueType() == MVT::f16 && !FullFP16) {
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@ -1628,7 +1631,7 @@ static bool isConjunctionDisjunctionTree(const SDValue Val, bool &CanNegate,
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/// depth to avoid stack overflow.
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static SDValue emitConjunctionDisjunctionTreeRec(SelectionDAG &DAG, SDValue Val,
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AArch64CC::CondCode &OutCC, bool Negate, SDValue CCOp,
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AArch64CC::CondCode Predicate, bool FullFP16 = false) {
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AArch64CC::CondCode Predicate) {
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// We're at a tree leaf, produce a conditional comparison operation.
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unsigned Opcode = Val->getOpcode();
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if (Opcode == ISD::SETCC) {
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@ -1654,8 +1657,7 @@ static SDValue emitConjunctionDisjunctionTreeRec(SelectionDAG &DAG, SDValue Val,
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ExtraCmp = emitComparison(LHS, RHS, CC, DL, DAG);
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else
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ExtraCmp = emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate,
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ExtraCC, DL, DAG,
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FullFP16);
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ExtraCC, DL, DAG);
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CCOp = ExtraCmp;
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Predicate = ExtraCC;
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}
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@ -1666,7 +1668,7 @@ static SDValue emitConjunctionDisjunctionTreeRec(SelectionDAG &DAG, SDValue Val,
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return emitComparison(LHS, RHS, CC, DL, DAG);
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// Otherwise produce a ccmp.
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return emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate, OutCC, DL,
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DAG, FullFP16);
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DAG);
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}
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assert((Opcode == ISD::AND || (Opcode == ISD::OR && Val->hasOneUse())) &&
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"Valid conjunction/disjunction tree");
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@ -1713,13 +1715,13 @@ static SDValue emitConjunctionDisjunctionTreeRec(SelectionDAG &DAG, SDValue Val,
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// the "flags to test" afterwards.
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AArch64CC::CondCode RHSCC;
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SDValue CmpR = emitConjunctionDisjunctionTreeRec(DAG, RHS, RHSCC, Negate,
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CCOp, Predicate, FullFP16);
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CCOp, Predicate);
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if (NegateOpsAndResult && !Negate)
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RHSCC = AArch64CC::getInvertedCondCode(RHSCC);
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// Emit LHS. We may need to negate it.
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SDValue CmpL = emitConjunctionDisjunctionTreeRec(DAG, LHS, OutCC,
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NegateOpsAndResult, CmpR,
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RHSCC, FullFP16);
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RHSCC);
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// If we transformed an OR to and AND then we have to negate the result
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// (or absorb the Negate parameter).
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if (NegateOpsAndResult && !Negate)
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@ -1731,21 +1733,20 @@ static SDValue emitConjunctionDisjunctionTreeRec(SelectionDAG &DAG, SDValue Val,
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/// of CCMP/CFCMP ops. See @ref AArch64CCMP.
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/// \see emitConjunctionDisjunctionTreeRec().
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static SDValue emitConjunctionDisjunctionTree(SelectionDAG &DAG, SDValue Val,
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AArch64CC::CondCode &OutCC,
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bool FullFP16 = false) {
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AArch64CC::CondCode &OutCC) {
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bool CanNegate;
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if (!isConjunctionDisjunctionTree(Val, CanNegate))
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return SDValue();
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return emitConjunctionDisjunctionTreeRec(DAG, Val, OutCC, false, SDValue(),
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AArch64CC::AL, FullFP16);
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AArch64CC::AL);
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}
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/// @}
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static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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SDValue &AArch64cc, SelectionDAG &DAG,
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const SDLoc &dl, bool FullFP16 = false) {
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const SDLoc &dl) {
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if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
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EVT VT = RHS.getValueType();
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uint64_t C = RHSC->getZExtValue();
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@ -1832,13 +1833,13 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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DAG.getValueType(MVT::i16));
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Cmp = emitComparison(SExt, DAG.getConstant(ValueofRHS, dl,
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RHS.getValueType()),
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CC, dl, DAG, FullFP16);
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CC, dl, DAG);
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AArch64CC = changeIntCCToAArch64CC(CC);
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}
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}
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if (!Cmp && (RHSC->isNullValue() || RHSC->isOne())) {
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if ((Cmp = emitConjunctionDisjunctionTree(DAG, LHS, AArch64CC, FullFP16))) {
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if ((Cmp = emitConjunctionDisjunctionTree(DAG, LHS, AArch64CC))) {
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if ((CC == ISD::SETNE) ^ RHSC->isNullValue())
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AArch64CC = AArch64CC::getInvertedCondCode(AArch64CC);
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}
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@ -1846,7 +1847,7 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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}
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if (!Cmp) {
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Cmp = emitComparison(LHS, RHS, CC, dl, DAG, FullFP16);
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Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
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AArch64CC = changeIntCCToAArch64CC(CC);
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}
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AArch64cc = DAG.getConstant(AArch64CC, dl, MVT_CC);
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@ -4040,8 +4041,7 @@ SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
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}
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SDValue CCVal;
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SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl,
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Subtarget->hasFullFP16());
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SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
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return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
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Cmp);
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}
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@ -4051,7 +4051,7 @@ SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
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// Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
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// clean. Some of them require two branches to implement.
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SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG, Subtarget->hasFullFP16());
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SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
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AArch64CC::CondCode CC1, CC2;
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changeFPCCToAArch64CC(CC, CC1, CC2);
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SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
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@ -4206,8 +4206,7 @@ SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
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if (LHS.getValueType().isInteger()) {
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SDValue CCVal;
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SDValue Cmp =
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getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl,
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Subtarget->hasFullFP16());
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getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
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// Note that we inverted the condition above, so we reverse the order of
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// the true and false operands here. This will allow the setcc to be
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@ -4221,7 +4220,7 @@ SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
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// If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
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// and do the comparison.
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SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG, Subtarget->hasFullFP16());
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SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
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AArch64CC::CondCode CC1, CC2;
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changeFPCCToAArch64CC(CC, CC1, CC2);
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@ -4387,9 +4386,7 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
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}
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SDValue CCVal;
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SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl,
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Subtarget->hasFullFP16());
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SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
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EVT VT = TVal.getValueType();
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return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
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}
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@ -4399,7 +4396,7 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
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LHS.getValueType() == MVT::f64);
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assert(LHS.getValueType() == RHS.getValueType());
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EVT VT = TVal.getValueType();
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SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG, Subtarget->hasFullFP16());
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SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
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// Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
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// clean. Some of them require two CSELs to implement.
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