A compiler writer's guide to <atomic>, minor update
llvm-svn: 115633
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@ -377,11 +377,17 @@ for the detailed definitions of each of these orderings).
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<p>
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On some platforms, the compiler vendor can offer some or even all of the above
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intrinsics at one or more weaker levels of memory synchronization. This might
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lead for example to not issuing an <tt>mfense</tt> instruction on the x86. If
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the compiler does not offer any given operation, at any given memory ordering
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lead for example to not issuing an <tt>mfense</tt> instruction on the x86.
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</p>
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<p>
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If the compiler does not offer any given operation, at any given memory ordering
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level, the library will automatically attempt to call the next highest memory
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ordering operation. This continues up to <tt>seq_cst</tt>, and if that doesn't
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exist, then the library takes over and does the job with a <tt>mutex</tt>.
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exist, then the library takes over and does the job with a <tt>mutex</tt>. This
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is a compile-time search & selection operation. At run time, the
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application will only see the few inlined assembly instructions for the selected
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intrinsic.
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</p>
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<p>
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