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Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for a 

case.  Also, the 0xFF hex literal involved in the shift for ESize64 should be
suffixed "ul" to preserve the shift result.

Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a
test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand().

llvm-svn: 101557
This commit is contained in:
Johnny Chen 2010-04-16 22:40:20 +00:00
parent ae4b5df817
commit b90b6f1a35
4 changed files with 29 additions and 5 deletions
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20
llvm/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
View File

@ -18,6 +18,7 @@
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
@ -777,3 +778,22 @@ void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum,
O << '#' << MI->getOperand(OpNum).getImm();
}
void ARMInstPrinter::printHex8ImmOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xff);
}
void ARMInstPrinter::printHex16ImmOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffff);
}
void ARMInstPrinter::printHex32ImmOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffffffff);
}
void ARMInstPrinter::printHex64ImmOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm());
}

8
llvm/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
View File

@ -104,10 +104,10 @@ public:
void printNoHashImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printHex8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) {}
void printHex16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) {}
void printHex32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) {}
void printHex64ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) {}
void printHex8ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printHex16ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printHex32ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printHex64ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O);
// FIXME: Implement.

3
llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -2104,7 +2104,7 @@ static uint64_t decodeN1VImm(uint32_t insn, ElemSize esize) {
case ESize64: {
for (unsigned i = 0; i < 8; ++i)
if ((Imm8 >> i) & 1)
Imm64 |= 0xFF << 8*i;
Imm64 |= 0xFFul << 8*i;
break;
}
default:
@ -2450,6 +2450,7 @@ static bool DisassembleN1RegModImmFrm(MCInst &MI, unsigned Opcode,
case ARM::VMOVv1i64:
case ARM::VMOVv2i64:
esize = ESize64;
break;
default:
assert(0 && "Unreachable code!");
return false;

3
llvm/test/MC/Disassembler/neon-tests.txt
View File

@ -18,6 +18,9 @@
# CHECK: vmov d0, d15
0x1f 0x01 0x2f 0xf2
# CHECK: vmov.i64 q6, #0xFF00FF00FF
0x75 0xde 0x81 0xf2
# CHECK: vmul.f32 d0, d0, d6
0x16 0x0d 0x00 0xf3