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Fix recognition of 16-bit bswap for C front-ends which emit the 

clobber registers in a different order.

llvm-svn: 97741
This commit is contained in:
Dan Gohman 2010-03-04 19:58:08 +00:00
parent 795667b424
commit b8ebd408da
2 changed files with 77 additions and 5 deletions
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15
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -9838,11 +9838,20 @@ bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
// rorw $$8, ${0:w} --> llvm.bswap.i16
if (CI->getType()->isIntegerTy(16) &&
AsmPieces.size() == 3 &&
AsmPieces[0] == "rorw" &&
(AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
AsmPieces[1] == "$$8," &&
AsmPieces[2] == "${0:w}" &&
IA->getConstraintString() == "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}") {
return LowerToBSwap(CI);
IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
AsmPieces.clear();
SplitString(IA->getConstraintString().substr(5), AsmPieces, ",");
std::sort(AsmPieces.begin(), AsmPieces.end());
if (AsmPieces.size() == 4 &&
AsmPieces[0] == "~{cc}" &&
AsmPieces[1] == "~{dirflag}" &&
AsmPieces[2] == "~{flags}" &&
AsmPieces[3] == "~{fpsr}") {
return LowerToBSwap(CI);
}
}
break;
case 3:

67
llvm/test/CodeGen/X86/bswap-inline-asm.ll
View File

@ -1,17 +1,80 @@
; RUN: llc < %s -march=x86-64 > %t
; RUN: not grep APP %t
; RUN: grep bswapq %t | count 2
; RUN: grep bswapl %t | count 1
; RUN: FileCheck %s < %t
; CHECK: foo:
; CHECK: bswapq
define i64 @foo(i64 %x) nounwind {
%asmtmp = tail call i64 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
ret i64 %asmtmp
}
; CHECK: bar:
; CHECK: bswapq
define i64 @bar(i64 %x) nounwind {
%asmtmp = tail call i64 asm "bswapq ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
ret i64 %asmtmp
}
; CHECK: pen:
; CHECK: bswapl
define i32 @pen(i32 %x) nounwind {
%asmtmp = tail call i32 asm "bswapl ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %x) nounwind
ret i32 %asmtmp
}
; CHECK: s16:
; CHECK: rolw $8,
define zeroext i16 @s16(i16 zeroext %x) nounwind {
%asmtmp = tail call i16 asm "rorw $$8, ${0:w}", "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i16 %x) nounwind
ret i16 %asmtmp
}
; CHECK: t16:
; CHECK: rolw $8,
define zeroext i16 @t16(i16 zeroext %x) nounwind {
%asmtmp = tail call i16 asm "rorw $$8, ${0:w}", "=r,0,~{cc},~{dirflag},~{fpsr},~{flags}"(i16 %x) nounwind
ret i16 %asmtmp
}
; CHECK: u16:
; CHECK: rolw $8,
define zeroext i16 @u16(i16 zeroext %x) nounwind {
%asmtmp = tail call i16 asm "rolw $$8, ${0:w}", "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i16 %x) nounwind
ret i16 %asmtmp
}
; CHECK: v16:
; CHECK: rolw $8,
define zeroext i16 @v16(i16 zeroext %x) nounwind {
%asmtmp = tail call i16 asm "rolw $$8, ${0:w}", "=r,0,~{cc},~{dirflag},~{fpsr},~{flags}"(i16 %x) nounwind
ret i16 %asmtmp
}
; CHECK: s32:
; CHECK: bswapl
define i32 @s32(i32 %x) nounwind {
%asmtmp = tail call i32 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %x) nounwind
ret i32 %asmtmp
}
; CHECK: t32:
; CHECK: bswapl
define i32 @t32(i32 %x) nounwind {
%asmtmp = tail call i32 asm "bswap $0", "=r,0,~{dirflag},~{flags},~{fpsr}"(i32 %x) nounwind
ret i32 %asmtmp
}
; CHECK: s64:
; CHECK: bswapq
define i64 @s64(i64 %x) nounwind {
%asmtmp = tail call i64 asm "bswap ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
ret i64 %asmtmp
}
; CHECK: t64:
; CHECK: bswapq
define i64 @t64(i64 %x) nounwind {
%asmtmp = tail call i64 asm "bswap ${0:q}", "=r,0,~{fpsr},~{dirflag},~{flags}"(i64 %x) nounwind
ret i64 %asmtmp
}