diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h
index dcd454e89491..22d01bfc8463 100644
--- a/llvm/include/llvm/Target/TargetMachine.h
+++ b/llvm/include/llvm/Target/TargetMachine.h
@@ -101,7 +101,7 @@ public:
   virtual const TargetSubtargetInfo *getSubtargetImpl() const {
     return nullptr;
   }
-  virtual TargetSubtargetInfo *getSubtargetImpl() {
+  TargetSubtargetInfo *getSubtargetImpl() {
     const TargetMachine *TM = this;
     return const_cast<TargetSubtargetInfo *>(TM->getSubtargetImpl());
   }
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.h b/llvm/lib/Target/ARM/ARMTargetMachine.h
index ae98c21e4b45..8b559682211d 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.h
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.h
@@ -33,7 +33,6 @@ public:
                        bool isLittle);
 
   const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
-  ARMSubtarget *getSubtargetImpl() override { return &Subtarget; }
 
   /// \brief Register ARM analysis passes with a pass manager.
   void addAnalysisPasses(PassManagerBase &PM) override;
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.h b/llvm/lib/Target/Mips/MipsTargetMachine.h
index 6d53274c18a7..eefd96ab4aea 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.h
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.h
@@ -44,10 +44,8 @@ public:
       return Subtarget;
     return &DefaultSubtarget;
   }
-  MipsSubtarget *getSubtargetImpl() override {
-    if (Subtarget)
-      return Subtarget;
-    return &DefaultSubtarget;
+  MipsSubtarget *getSubtargetImpl() {
+    return static_cast<MipsSubtarget *>(TargetMachine::getSubtargetImpl());
   }
 
   /// \brief Reset the subtarget for the Mips target.
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.h b/llvm/lib/Target/PowerPC/PPCTargetMachine.h
index 653615aeadde..9bda22a354dd 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.h
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.h
@@ -33,7 +33,6 @@ public:
                    CodeGenOpt::Level OL, bool is64Bit);
 
   const PPCSubtarget *getSubtargetImpl() const override { return &Subtarget; }
-  PPCSubtarget *getSubtargetImpl() override { return &Subtarget; }
 
   // Pass Pipeline Configuration
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.h b/llvm/lib/Target/Sparc/SparcTargetMachine.h
index 2e0c778464d3..62f088b14812 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.h
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.h
@@ -29,7 +29,10 @@ public:
                      CodeGenOpt::Level OL, bool is64bit);
 
   const SparcSubtarget *getSubtargetImpl() const override { return &Subtarget; }
-  SparcSubtarget *getSubtargetImpl() override { return &Subtarget; }
+
+  SparcSubtarget *getSubtargetImpl() {
+    return static_cast<SparcSubtarget *>(TargetMachine::getSubtargetImpl());
+  }
 
   // Pass Pipeline Configuration
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
diff --git a/llvm/lib/Target/X86/X86TargetMachine.h b/llvm/lib/Target/X86/X86TargetMachine.h
index 4bdb5084075f..633c57103159 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.h
+++ b/llvm/lib/Target/X86/X86TargetMachine.h
@@ -32,7 +32,10 @@ public:
                    Reloc::Model RM, CodeModel::Model CM,
                    CodeGenOpt::Level OL);
   const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; }
-  X86Subtarget *getSubtargetImpl() override { return &Subtarget; }
+
+  X86Subtarget *getSubtargetImpl() {
+    return static_cast<X86Subtarget *>(TargetMachine::getSubtargetImpl());
+  }
 
   /// \brief Register X86 analysis passes with a pass manager.
   void addAnalysisPasses(PassManagerBase &PM) override;