diff --git a/llvm/docs/GlobalISel.rst b/llvm/docs/GlobalISel.rst
index 52952d014c47..c124911978c5 100644
--- a/llvm/docs/GlobalISel.rst
+++ b/llvm/docs/GlobalISel.rst
@@ -304,6 +304,11 @@ As opposed to SelectionDAG, there are no legalization phases.  In particular,
 Legalization is iterative, and all state is contained in GMIR.  To maintain the
 validity of the intermediate code, instructions are introduced:
 
+* ``G_MERGE_VALUES`` --- concatenate multiple registers of the same
+  size into a single wider register.
+
+* ``G_UNMERGE_VALUES`` --- extract multiple registers of the same size
+  from a single wider register.
 
 * ``G_EXTRACT`` --- extract a simple register (as contiguous sequences of bits)
   from a single wider register.
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index e3136b138090..6e6b5820d4b6 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -511,6 +511,7 @@ def G_INSERT : Instruction {
   let hasSideEffects = 0;
 }
 
+/// Concatenante multiple registers of the same size into a wider register.
 def G_MERGE_VALUES : Instruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins variable_ops);