[CodeGen] Detect impossible partial write conditions more reliably.
Whether a partial write is tautological/unsatisfiable not only
depends on the access domain, but also on the domain covered
by its node in the AST.
In the example below, there are two instances of Stmt_cond_false. It may have a partial write access that is not executed in instance Stmt_cond_false(0).
for (int c0 = 0; c0 < tmp5; c0 += 1) {
Stmt_for_body344(c0);
if (tmp5 >= c0 + 2)
Stmt_cond_false(c0);
Stmt_cond_end(c0);
}
if (tmp5 <= 0) {
Stmt_for_body344(0);
Stmt_cond_false(0);
Stmt_cond_end(0);
}
Isl cannot derive a subscript for an array element that is never accessed.
This caused an error in that no subscript expression has been generated
in IslNodeBuilder::createNewAccesses, but BlockGenerator expected one
to exist because there is an execution of that write, just not in that
ast node.
Fixed by instead of determining whether the access domain is empty,
inspect whether isl generated a constant "false" ast expression in
the current ast node.
This should fix a compiler crash of the aosp buildbot.
llvm-svn: 311663
This commit is contained in:
Michael Kruse
parent
b0eb5fb317
commit
b795bfc0d4
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@ -601,11 +601,6 @@ void BlockGenerator::generateConditionalExecution(
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const std::function<void()> &GenThenFunc) {
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isl::set StmtDom = Stmt.getDomain();
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// Don't call GenThenFunc if it is never executed. An ast index expression
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// might not be defined in this case.
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if (Subdomain.is_empty())
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return;
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// If the condition is a tautology, don't generate a condition around the
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// code.
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bool IsPartialWrite =
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@ -618,6 +613,13 @@ void BlockGenerator::generateConditionalExecution(
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// Generate the condition.
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Value *Cond = buildContainsCondition(Stmt, Subdomain);
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// Don't call GenThenFunc if it is never executed. An ast index expression
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// might not be defined in this case.
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if (auto *Const = dyn_cast<ConstantInt>(Cond))
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if (Const->isZero())
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return;
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BasicBlock *HeadBlock = Builder.GetInsertBlock();
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StringRef BlockName = HeadBlock->getName();
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@ -0,0 +1,59 @@
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; RUN: opt %loadPolly -polly-import-jscop -polly-import-jscop-postfix=transformed -polly-codegen -S < %s | FileCheck %s
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;
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; The isl scheduler isolates %cond.false into two instances.
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; A partial write access in one of the instances was never executed,
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; which caused problems when querying for its index expression, which
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; is not available in that case.
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;
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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define void @partial_write_impossible_restriction() {
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entry:
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br i1 undef, label %invoke.cont258, label %cond.true.i.i.i.i1007
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cond.true.i.i.i.i1007:
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br label %invoke.cont258
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invoke.cont258:
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%.pn = phi i32* [ null, %cond.true.i.i.i.i1007 ], [ null, %entry ]
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br label %invoke.cont274
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invoke.cont274: ; preds = %invoke.cont258
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%tmp4 = load i32*, i32** undef
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%tmp5 = load i32, i32* undef
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%tmp6 = zext i32 %tmp5 to i64
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%tmp7 = sext i32 %tmp5 to i64
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br label %for.body344
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for.body344: ; preds = %cond.end, %invoke.cont274
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%indvars.iv1602 = phi i64 [ 0, %invoke.cont274 ], [ %indvars.iv.next1603, %cond.end ]
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%indvars.iv.next1603 = add nuw nsw i64 %indvars.iv1602, 1
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%cmp347 = icmp eq i64 %indvars.iv.next1603, %tmp6
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br i1 %cmp347, label %cond.end, label %cond.false
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cond.false: ; preds = %for.body344
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%add.ptr.i1128 = getelementptr inbounds i32, i32* %tmp4, i64 %indvars.iv.next1603
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%cond.in.sroa.speculate.load.cond.false = load i32, i32* %add.ptr.i1128
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br label %cond.end
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cond.end: ; preds = %cond.false, %for.body344
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%cond.in.sroa.speculated = phi i32 [ %cond.in.sroa.speculate.load.cond.false, %cond.false ], [ undef, %for.body344 ]
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%add.ptr.i1132 = getelementptr inbounds i32, i32* %.pn, i64 %indvars.iv1602
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store i32 undef, i32* %add.ptr.i1132
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%cmp342 = icmp slt i64 %indvars.iv.next1603, %tmp7
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br i1 %cmp342, label %for.body344, label %if.then.i.i1141.loopexit
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if.then.i.i1141.loopexit: ; preds = %cond.end
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ret void
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}
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; CHECK-LABEL: polly.stmt.cond.false:
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; CHECK: %polly.access..pn2 = getelementptr i32, i32* %.pn, i64 %polly.indvar
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; CHECK: store i32 %cond.in.sroa.speculate.load.cond.false_p_scalar_, i32* %polly.access..pn2, !alias.scope !0, !noalias !2
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; CHECK: br label %polly.merge
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; CHECK-LABEL: polly.stmt.cond.false11:
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; CHECK: %polly.access..pn14 = getelementptr i32, i32* %.pn, i64 0
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; CHECK: store i32 %cond.in.sroa.speculate.load.cond.false_p_scalar_13, i32* %polly.access..pn14, !alias.scope !0, !noalias !2
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; CHECK: br label %polly.stmt.cond.end15
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@ -0,0 +1,59 @@
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{
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"arrays" : [
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{
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"name" : "MemRef_tmp4",
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"sizes" : [ "*" ],
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"type" : "i32"
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},
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{
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"name" : "MemRef__pn",
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"sizes" : [ "*" ],
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"type" : "i32"
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}
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],
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"context" : "[tmp5] -> { : -2147483648 <= tmp5 <= 2147483647 }",
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"name" : "%for.body344---%if.then.i.i1141.loopexit",
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"statements" : [
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{
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"accesses" : [
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{
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"kind" : "write",
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"relation" : "[tmp5] -> { Stmt_for_body344[i0] -> MemRef_cond_in_sroa_speculated__phi[] }"
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}
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],
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"domain" : "[tmp5] -> { Stmt_for_body344[i0] : 0 <= i0 < tmp5; Stmt_for_body344[0] : tmp5 <= 0 }",
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"name" : "Stmt_for_body344",
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"schedule" : "[tmp5] -> { Stmt_for_body344[i0] -> [i0, 0] : i0 < tmp5; Stmt_for_body344[0] -> [0, 0] : tmp5 <= 0 }"
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},
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{
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"accesses" : [
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{
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"kind" : "read",
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"relation" : "[tmp5] -> { Stmt_cond_false[i0] -> MemRef_tmp4[1 + i0] }"
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},
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{
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"kind" : "write",
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"relation" : "[tmp5] -> { Stmt_cond_false[i0] -> MemRef_cond_in_sroa_speculated__phi[] }"
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}
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],
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"domain" : "[tmp5] -> { Stmt_cond_false[i0] : 0 <= i0 <= -2 + tmp5; Stmt_cond_false[0] : tmp5 <= 0 }",
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"name" : "Stmt_cond_false",
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"schedule" : "[tmp5] -> { Stmt_cond_false[i0] -> [i0, 1] : i0 <= -2 + tmp5; Stmt_cond_false[0] -> [0, 1] : tmp5 <= 0 }"
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},
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{
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"accesses" : [
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{
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"kind" : "read",
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"relation" : "[tmp5] -> { Stmt_cond_end[i0] -> MemRef_cond_in_sroa_speculated__phi[] }"
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},
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{
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"kind" : "write",
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"relation" : "[tmp5] -> { Stmt_cond_end[i0] -> MemRef__pn[i0] }"
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}
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],
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"domain" : "[tmp5] -> { Stmt_cond_end[i0] : 0 <= i0 < tmp5; Stmt_cond_end[0] : tmp5 <= 0 }",
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"name" : "Stmt_cond_end",
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"schedule" : "[tmp5] -> { Stmt_cond_end[i0] -> [i0, 2] : i0 < tmp5; Stmt_cond_end[0] -> [0, 2] : tmp5 <= 0 }"
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}
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]
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}
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@ -0,0 +1,59 @@
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{
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"arrays" : [
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{
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"name" : "MemRef_tmp4",
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"sizes" : [ "*" ],
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"type" : "i32"
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},
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{
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"name" : "MemRef__pn",
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"sizes" : [ "*" ],
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"type" : "i32"
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}
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],
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"context" : "[tmp5] -> { : -2147483648 <= tmp5 <= 2147483647 }",
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"name" : "%for.body344---%if.then.i.i1141.loopexit",
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"statements" : [
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{
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"accesses" : [
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{
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"kind" : "write",
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"relation" : "[tmp5] -> { Stmt_for_body344[-1 + tmp5] -> MemRef__pn[-1 + tmp5] }"
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}
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],
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"domain" : "[tmp5] -> { Stmt_for_body344[i0] : 0 <= i0 < tmp5; Stmt_for_body344[0] : tmp5 <= 0 }",
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"name" : "Stmt_for_body344",
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"schedule" : "[tmp5] -> { Stmt_for_body344[i0] -> [i0, 0] : i0 < tmp5; Stmt_for_body344[0] -> [0, 0] : tmp5 <= 0 }"
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},
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{
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"accesses" : [
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{
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"kind" : "read",
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"relation" : "[tmp5] -> { Stmt_cond_false[i0] -> MemRef_tmp4[1 + i0] }"
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},
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{
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"kind" : "write",
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"relation" : "[tmp5] -> { Stmt_cond_false[i0] -> MemRef__pn[i0] : i0 <= -2 + tmp5; Stmt_cond_false[0] -> MemRef__pn[0] : tmp5 <= 0 }"
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}
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],
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"domain" : "[tmp5] -> { Stmt_cond_false[i0] : 0 <= i0 <= -2 + tmp5; Stmt_cond_false[0] : tmp5 <= 0 }",
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"name" : "Stmt_cond_false",
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"schedule" : "[tmp5] -> { Stmt_cond_false[i0] -> [i0, 1] : i0 <= -2 + tmp5; Stmt_cond_false[0] -> [0, 1] : tmp5 <= 0 }"
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},
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{
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"accesses" : [
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{
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"kind" : "read",
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"relation" : "[tmp5] -> { Stmt_cond_end[i0] -> MemRef__pn[i0] }"
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},
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{
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"kind" : "write",
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"relation" : "[tmp5] -> { Stmt_cond_end[i0] -> MemRef__pn[i0] }"
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}
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],
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"domain" : "[tmp5] -> { Stmt_cond_end[i0] : 0 <= i0 < tmp5; Stmt_cond_end[0] : tmp5 <= 0 }",
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"name" : "Stmt_cond_end",
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"schedule" : "[tmp5] -> { Stmt_cond_end[i0] -> [i0, 2] : i0 < tmp5; Stmt_cond_end[0] -> [0, 2] : tmp5 <= 0 }"
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}
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]
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}
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