[X86] Take advantage of the lzcnt instruction on btver2 architectures when ORing comparisons to zero.
This change adds transformations such as: zext(or(setcc(eq, (cmp x, 0)), setcc(eq, (cmp y, 0)))) To: srl(or(ctlz(x), ctlz(y)), log2(bitsize(x)) This optimisation is beneficial on Jaguar architecture only, where lzcnt has a good reciprocal throughput. Other architectures such as Intel's Haswell/Broadwell or AMD's Bulldozer/PileDriver do not benefit from it. For this reason the change also adds a "HasFastLZCNT" feature which gets enabled for Jaguar. Differential Revision: https://reviews.llvm.org/D23446 llvm-svn: 284248
This commit is contained in:
Pierre Gousseau
parent
6d6eca5cdc
commit
b6d652adb5
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@ -262,6 +262,12 @@ def FeatureFastScalarFSQRT
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def FeatureFastVectorFSQRT
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: SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT",
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"true", "Vector SQRT is fast (disable Newton-Raphson)">;
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// If lzcnt has equivalent latency/throughput to most simple integer ops, it can
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// be used to replace test/set sequences.
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def FeatureFastLZCNT
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: SubtargetFeature<
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"fast-lzcnt", "HasFastLZCNT", "true",
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"LZCNT instructions are as fast as most simple integer ops">;
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//===----------------------------------------------------------------------===//
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// X86 processors supported.
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@ -646,6 +652,7 @@ def : ProcessorModel<"btver2", BtVer2Model, [
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FeatureF16C,
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FeatureMOVBE,
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FeatureLZCNT,
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FeatureFastLZCNT,
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FeaturePOPCNT,
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FeatureXSAVE,
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FeatureXSAVEOPT,
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@ -4178,6 +4178,10 @@ bool X86TargetLowering::isCheapToSpeculateCtlz() const {
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return Subtarget.hasLZCNT();
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}
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bool X86TargetLowering::isCtlzFast() const {
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return Subtarget.hasFastLZCNT();
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}
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bool X86TargetLowering::hasAndNotCompare(SDValue Y) const {
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if (!Subtarget.hasBMI())
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return false;
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@ -29090,6 +29094,113 @@ static SDValue combineLogicBlendIntoPBLENDV(SDNode *N, SelectionDAG &DAG,
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return DAG.getBitcast(VT, Mask);
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}
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// Helper function for combineOrCmpEqZeroToCtlzSrl
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// Transforms:
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// seteq(cmp x, 0)
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// into:
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// srl(ctlz x), log2(bitsize(x))
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// Input pattern is checked by caller.
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SDValue lowerX86CmpEqZeroToCtlzSrl(SDValue Op, EVT ExtTy, SelectionDAG &DAG) {
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SDValue Cmp = Op.getOperand(1);
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EVT VT = Cmp.getOperand(0).getValueType();
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unsigned Log2b = Log2_32(VT.getSizeInBits());
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SDLoc dl(Op);
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SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Cmp->getOperand(0));
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// The result of the shift is true or false, and on X86, the 32-bit
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// encoding of shr and lzcnt is more desirable.
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SDValue Trunc = DAG.getZExtOrTrunc(Clz, dl, MVT::i32);
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SDValue Scc = DAG.getNode(ISD::SRL, dl, MVT::i32, Trunc,
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DAG.getConstant(Log2b, dl, VT));
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return DAG.getZExtOrTrunc(Scc, dl, ExtTy);
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}
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// Try to transform:
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// zext(or(setcc(eq, (cmp x, 0)), setcc(eq, (cmp y, 0))))
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// into:
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// srl(or(ctlz(x), ctlz(y)), log2(bitsize(x))
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// Will also attempt to match more generic cases, eg:
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// zext(or(or(setcc(eq, cmp 0), setcc(eq, cmp 0)), setcc(eq, cmp 0)))
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// Only applies if the target supports the FastLZCNT feature.
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static SDValue combineOrCmpEqZeroToCtlzSrl(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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if (DCI.isBeforeLegalize() || !Subtarget.getTargetLowering()->isCtlzFast())
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return SDValue();
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auto isORCandidate = [](SDValue N) {
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return (N->getOpcode() == ISD::OR && N->hasOneUse());
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};
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// Check the zero extend is extending to 32-bit or more. The code generated by
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// srl(ctlz) for 16-bit or less variants of the pattern would require extra
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// instructions to clear the upper bits.
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if (!N->hasOneUse() || !N->getSimpleValueType(0).bitsGE(MVT::i32) ||
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!isORCandidate(N->getOperand(0)))
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return SDValue();
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// Check the node matches: setcc(eq, cmp 0)
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auto isSetCCCandidate = [](SDValue N) {
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return N->getOpcode() == X86ISD::SETCC && N->hasOneUse() &&
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X86::CondCode(N->getConstantOperandVal(0)) == X86::COND_E &&
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N->getOperand(1).getOpcode() == X86ISD::CMP &&
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N->getOperand(1).getConstantOperandVal(1) == 0 &&
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N->getOperand(1).getValueType().bitsGE(MVT::i32);
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};
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SDNode *OR = N->getOperand(0).getNode();
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SDValue LHS = OR->getOperand(0);
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SDValue RHS = OR->getOperand(1);
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// Save nodes matching or(or, setcc(eq, cmp 0)).
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SmallVector<SDNode *, 2> ORNodes;
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while (((isORCandidate(LHS) && isSetCCCandidate(RHS)) ||
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(isORCandidate(RHS) && isSetCCCandidate(LHS)))) {
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ORNodes.push_back(OR);
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OR = (LHS->getOpcode() == ISD::OR) ? LHS.getNode() : RHS.getNode();
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LHS = OR->getOperand(0);
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RHS = OR->getOperand(1);
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}
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// The last OR node should match or(setcc(eq, cmp 0), setcc(eq, cmp 0)).
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if (!(isSetCCCandidate(LHS) && isSetCCCandidate(RHS)) ||
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!isORCandidate(SDValue(OR, 0)))
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return SDValue();
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// We have a or(setcc(eq, cmp 0), setcc(eq, cmp 0)) pattern, try to lower it
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// to
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// or(srl(ctlz),srl(ctlz)).
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// The dag combiner can then fold it into:
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// srl(or(ctlz, ctlz)).
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EVT VT = OR->getValueType(0);
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SDValue NewLHS = lowerX86CmpEqZeroToCtlzSrl(LHS, VT, DAG);
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SDValue Ret, NewRHS;
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if (NewLHS && (NewRHS = lowerX86CmpEqZeroToCtlzSrl(RHS, VT, DAG)))
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Ret = DAG.getNode(ISD::OR, SDLoc(OR), VT, NewLHS, NewRHS);
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if (!Ret)
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return SDValue();
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// Try to lower nodes matching the or(or, setcc(eq, cmp 0)) pattern.
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while (ORNodes.size() > 0) {
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OR = ORNodes.pop_back_val();
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LHS = OR->getOperand(0);
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RHS = OR->getOperand(1);
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// Swap rhs with lhs to match or(setcc(eq, cmp, 0), or).
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if (RHS->getOpcode() == ISD::OR)
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std::swap(LHS, RHS);
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EVT VT = OR->getValueType(0);
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SDValue NewRHS = lowerX86CmpEqZeroToCtlzSrl(RHS, VT, DAG);
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if (!NewRHS)
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return SDValue();
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Ret = DAG.getNode(ISD::OR, SDLoc(OR), VT, Ret, NewRHS);
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}
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if (Ret)
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Ret = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0), Ret);
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return Ret;
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}
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static SDValue combineOr(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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@ -31121,6 +31232,9 @@ static SDValue combineZext(SDNode *N, SelectionDAG &DAG,
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if (SDValue NewAdd = promoteExtBeforeAdd(N, DAG, Subtarget))
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return NewAdd;
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if (SDValue R = combineOrCmpEqZeroToCtlzSrl(N, DAG, DCI, Subtarget))
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return R;
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return SDValue();
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}
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@ -771,6 +771,8 @@ namespace llvm {
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bool isCheapToSpeculateCtlz() const override;
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bool isCtlzFast() const override;
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bool hasBitPreservingFPLogic(EVT VT) const override {
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return VT == MVT::f32 || VT == MVT::f64 || VT.isVector();
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}
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@ -890,6 +890,7 @@ def CallImmAddr : Predicate<"Subtarget->isLegalToCallImmediateAddr()">;
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def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
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def NotSlowIncDec : Predicate<"!Subtarget->slowIncDec()">;
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def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">;
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def HasFastLZCNT : Predicate<"Subtarget->hasFastLZCNT()">;
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def HasMFence : Predicate<"Subtarget->hasMFence()">;
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//===----------------------------------------------------------------------===//
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@ -284,6 +284,7 @@ void X86Subtarget::initializeEnvironment() {
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HasFastPartialYMMWrite = false;
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HasFastScalarFSQRT = false;
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HasFastVectorFSQRT = false;
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HasFastLZCNT = false;
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HasSlowDivide32 = false;
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HasSlowDivide64 = false;
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PadShortFunctions = false;
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@ -215,6 +215,9 @@ protected:
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/// 64-bit divisions and should be used when possible.
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bool HasSlowDivide64;
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/// True if LZCNT instruction is fast.
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bool HasFastLZCNT;
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/// True if the short functions should be padded to prevent
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/// a stall when returning too early.
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bool PadShortFunctions;
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@ -444,6 +447,7 @@ public:
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bool hasFastPartialYMMWrite() const { return HasFastPartialYMMWrite; }
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bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
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bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
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bool hasFastLZCNT() const { return HasFastLZCNT; }
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bool hasSlowDivide32() const { return HasSlowDivide32; }
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bool hasSlowDivide64() const { return HasSlowDivide64; }
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bool padShortFunctions() const { return PadShortFunctions; }
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@ -0,0 +1,341 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; Test patterns which generates lzcnt instructions.
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; Eg: zext(or(setcc(cmp), setcc(cmp))) -> shr(or(lzcnt, lzcnt))
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=btver2 | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=btver2 -mattr=-fast-lzcnt | FileCheck --check-prefix=NOFASTLZCNT %s
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; Test one 32-bit input, output is 32-bit, no transformations expected.
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define i32 @test_zext_cmp0(i32 %a) {
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; CHECK-LABEL: test_zext_cmp0:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: testl %edi, %edi
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp0:
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; NOFASTLZCNT: # BB#0: # %entry
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; NOFASTLZCNT-NEXT: xorl %eax, %eax
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; NOFASTLZCNT-NEXT: testl %edi, %edi
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; NOFASTLZCNT-NEXT: sete %al
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; NOFASTLZCNT-NEXT: retq
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entry:
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%cmp = icmp eq i32 %a, 0
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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; Test two 32-bit inputs, output is 32-bit.
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define i32 @test_zext_cmp1(i32 %a, i32 %b) {
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; CHECK-LABEL: test_zext_cmp1:
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; CHECK: # BB#0:
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; CHECK-NEXT: lzcntl %edi, %ecx
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; CHECK-NEXT: lzcntl %esi, %eax
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: shrl $5, %eax
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; CHECK-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp1:
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; NOFASTLZCNT: # BB#0:
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; NOFASTLZCNT-NEXT: testl %edi, %edi
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; NOFASTLZCNT-NEXT: sete %al
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; NOFASTLZCNT-NEXT: testl %esi, %esi
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; NOFASTLZCNT-NEXT: sete %cl
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; NOFASTLZCNT-NEXT: orb %al, %cl
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; NOFASTLZCNT-NEXT: movzbl %cl, %eax
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; NOFASTLZCNT-NEXT: retq
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%cmp = icmp eq i32 %a, 0
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%cmp1 = icmp eq i32 %b, 0
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%or = or i1 %cmp, %cmp1
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%lor.ext = zext i1 %or to i32
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ret i32 %lor.ext
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}
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; Test two 64-bit inputs, output is 64-bit.
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define i64 @test_zext_cmp2(i64 %a, i64 %b) {
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; CHECK-LABEL: test_zext_cmp2:
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; CHECK: # BB#0:
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; CHECK-NEXT: lzcntq %rdi, %rcx
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; CHECK-NEXT: lzcntq %rsi, %rax
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: shrl $6, %eax
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; CHECK-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp2:
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; NOFASTLZCNT: # BB#0:
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; NOFASTLZCNT-NEXT: testq %rdi, %rdi
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; NOFASTLZCNT-NEXT: sete %al
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; NOFASTLZCNT-NEXT: testq %rsi, %rsi
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; NOFASTLZCNT-NEXT: sete %cl
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; NOFASTLZCNT-NEXT: orb %al, %cl
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; NOFASTLZCNT-NEXT: movzbl %cl, %eax
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; NOFASTLZCNT-NEXT: retq
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%cmp = icmp eq i64 %a, 0
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%cmp1 = icmp eq i64 %b, 0
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%or = or i1 %cmp, %cmp1
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%lor.ext = zext i1 %or to i64
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ret i64 %lor.ext
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}
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; Test two 16-bit inputs, output is 16-bit.
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; The transform is disabled for the 16-bit case, as we still have to clear the
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; upper 16-bits, adding one more instruction.
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define i16 @test_zext_cmp3(i16 %a, i16 %b) {
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; CHECK-LABEL: test_zext_cmp3:
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; CHECK: # BB#0:
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; CHECK-NEXT: testw %di, %di
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: testw %si, %si
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; CHECK-NEXT: sete %cl
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; CHECK-NEXT: orb %al, %cl
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; CHECK-NEXT: movzbl %cl, %eax
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; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
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; CHECK-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp3:
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; NOFASTLZCNT: # BB#0:
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; NOFASTLZCNT-NEXT: testw %di, %di
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; NOFASTLZCNT-NEXT: sete %al
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; NOFASTLZCNT-NEXT: testw %si, %si
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; NOFASTLZCNT-NEXT: sete %cl
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; NOFASTLZCNT-NEXT: orb %al, %cl
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; NOFASTLZCNT-NEXT: movzbl %cl, %eax
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; NOFASTLZCNT-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
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; NOFASTLZCNT-NEXT: retq
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%cmp = icmp eq i16 %a, 0
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%cmp1 = icmp eq i16 %b, 0
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%or = or i1 %cmp, %cmp1
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%lor.ext = zext i1 %or to i16
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ret i16 %lor.ext
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}
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; Test two 32-bit inputs, output is 64-bit.
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define i64 @test_zext_cmp4(i32 %a, i32 %b) {
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; CHECK-LABEL: test_zext_cmp4:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: lzcntl %edi, %ecx
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; CHECK-NEXT: lzcntl %esi, %eax
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: shrl $5, %eax
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; CHECK-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp4:
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; NOFASTLZCNT: # BB#0: # %entry
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; NOFASTLZCNT-NEXT: testl %edi, %edi
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; NOFASTLZCNT-NEXT: sete %al
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; NOFASTLZCNT-NEXT: testl %esi, %esi
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; NOFASTLZCNT-NEXT: sete %cl
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; NOFASTLZCNT-NEXT: orb %al, %cl
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; NOFASTLZCNT-NEXT: movzbl %cl, %eax
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; NOFASTLZCNT-NEXT: retq
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entry:
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%cmp = icmp eq i32 %a, 0
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%cmp1 = icmp eq i32 %b, 0
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%0 = or i1 %cmp, %cmp1
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%conv = zext i1 %0 to i64
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ret i64 %conv
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}
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; Test two 64-bit inputs, output is 32-bit.
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define i32 @test_zext_cmp5(i64 %a, i64 %b) {
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; CHECK-LABEL: test_zext_cmp5:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: lzcntq %rdi, %rcx
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; CHECK-NEXT: lzcntq %rsi, %rax
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; CHECK-NEXT: orl %ecx, %eax
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; CHECK-NEXT: shrl $6, %eax
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; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill>
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; CHECK-NEXT: retq
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;
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; NOFASTLZCNT-LABEL: test_zext_cmp5:
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; NOFASTLZCNT: # BB#0: # %entry
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; NOFASTLZCNT-NEXT: testq %rdi, %rdi
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; NOFASTLZCNT-NEXT: sete %al
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; NOFASTLZCNT-NEXT: testq %rsi, %rsi
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; NOFASTLZCNT-NEXT: sete %cl
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; NOFASTLZCNT-NEXT: orb %al, %cl
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; NOFASTLZCNT-NEXT: movzbl %cl, %eax
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; NOFASTLZCNT-NEXT: retq
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entry:
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%cmp = icmp eq i64 %a, 0
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%cmp1 = icmp eq i64 %b, 0
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%0 = or i1 %cmp, %cmp1
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%lor.ext = zext i1 %0 to i32
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ret i32 %lor.ext
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}
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; Test three 32-bit inputs, output is 32-bit.
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define i32 @test_zext_cmp6(i32 %a, i32 %b, i32 %c) {
|
||||
; CHECK-LABEL: test_zext_cmp6:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: lzcntl %edi, %eax
|
||||
; CHECK-NEXT: lzcntl %esi, %ecx
|
||||
; CHECK-NEXT: orl %eax, %ecx
|
||||
; CHECK-NEXT: lzcntl %edx, %eax
|
||||
; CHECK-NEXT: orl %ecx, %eax
|
||||
; CHECK-NEXT: shrl $5, %eax
|
||||
; CHECK-NEXT: retq
|
||||
;
|
||||
; NOFASTLZCNT-LABEL: test_zext_cmp6:
|
||||
; NOFASTLZCNT: # BB#0: # %entry
|
||||
; NOFASTLZCNT-NEXT: testl %edi, %edi
|
||||
; NOFASTLZCNT-NEXT: sete %al
|
||||
; NOFASTLZCNT-NEXT: testl %esi, %esi
|
||||
; NOFASTLZCNT-NEXT: sete %cl
|
||||
; NOFASTLZCNT-NEXT: orb %al, %cl
|
||||
; NOFASTLZCNT-NEXT: testl %edx, %edx
|
||||
; NOFASTLZCNT-NEXT: sete %al
|
||||
; NOFASTLZCNT-NEXT: orb %cl, %al
|
||||
; NOFASTLZCNT-NEXT: movzbl %al, %eax
|
||||
; NOFASTLZCNT-NEXT: retq
|
||||
entry:
|
||||
%cmp = icmp eq i32 %a, 0
|
||||
%cmp1 = icmp eq i32 %b, 0
|
||||
%or.cond = or i1 %cmp, %cmp1
|
||||
%cmp2 = icmp eq i32 %c, 0
|
||||
%.cmp2 = or i1 %or.cond, %cmp2
|
||||
%lor.ext = zext i1 %.cmp2 to i32
|
||||
ret i32 %lor.ext
|
||||
}
|
||||
|
||||
; Test three 32-bit inputs, output is 32-bit, but compared to test_zext_cmp6 test,
|
||||
; %.cmp2 inputs' order is inverted.
|
||||
define i32 @test_zext_cmp7(i32 %a, i32 %b, i32 %c) {
|
||||
; CHECK-LABEL: test_zext_cmp7:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: lzcntl %edi, %eax
|
||||
; CHECK-NEXT: lzcntl %esi, %ecx
|
||||
; CHECK-NEXT: orl %eax, %ecx
|
||||
; CHECK-NEXT: lzcntl %edx, %eax
|
||||
; CHECK-NEXT: orl %ecx, %eax
|
||||
; CHECK-NEXT: shrl $5, %eax
|
||||
; CHECK-NEXT: retq
|
||||
;
|
||||
; NOFASTLZCNT-LABEL: test_zext_cmp7:
|
||||
; NOFASTLZCNT: # BB#0: # %entry
|
||||
; NOFASTLZCNT-NEXT: testl %edi, %edi
|
||||
; NOFASTLZCNT-NEXT: sete %al
|
||||
; NOFASTLZCNT-NEXT: testl %esi, %esi
|
||||
; NOFASTLZCNT-NEXT: sete %cl
|
||||
; NOFASTLZCNT-NEXT: orb %al, %cl
|
||||
; NOFASTLZCNT-NEXT: testl %edx, %edx
|
||||
; NOFASTLZCNT-NEXT: sete %al
|
||||
; NOFASTLZCNT-NEXT: orb %cl, %al
|
||||
; NOFASTLZCNT-NEXT: movzbl %al, %eax
|
||||
; NOFASTLZCNT-NEXT: retq
|
||||
entry:
|
||||
%cmp = icmp eq i32 %a, 0
|
||||
%cmp1 = icmp eq i32 %b, 0
|
||||
%or.cond = or i1 %cmp, %cmp1
|
||||
%cmp2 = icmp eq i32 %c, 0
|
||||
%.cmp2 = or i1 %cmp2, %or.cond
|
||||
%lor.ext = zext i1 %.cmp2 to i32
|
||||
ret i32 %lor.ext
|
||||
}
|
||||
|
||||
; Test four 32-bit inputs, output is 32-bit.
|
||||
define i32 @test_zext_cmp8(i32 %a, i32 %b, i32 %c, i32 %d) {
|
||||
; CHECK-LABEL: test_zext_cmp8:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: lzcntl %edi, %eax
|
||||
; CHECK-NEXT: lzcntl %esi, %esi
|
||||
; CHECK-NEXT: lzcntl %edx, %edx
|
||||
; CHECK-NEXT: orl %eax, %esi
|
||||
; CHECK-NEXT: lzcntl %ecx, %eax
|
||||
; CHECK-NEXT: orl %edx, %eax
|
||||
; CHECK-NEXT: orl %esi, %eax
|
||||
; CHECK-NEXT: shrl $5, %eax
|
||||
; CHECK-NEXT: retq
|
||||
;
|
||||
; NOFASTLZCNT-LABEL: test_zext_cmp8:
|
||||
; NOFASTLZCNT: # BB#0: # %entry
|
||||
; NOFASTLZCNT-NEXT: testl %edi, %edi
|
||||
; NOFASTLZCNT-NEXT: sete %dil
|
||||
; NOFASTLZCNT-NEXT: testl %esi, %esi
|
||||
; NOFASTLZCNT-NEXT: sete %al
|
||||
; NOFASTLZCNT-NEXT: orb %dil, %al
|
||||
; NOFASTLZCNT-NEXT: testl %edx, %edx
|
||||
; NOFASTLZCNT-NEXT: sete %dl
|
||||
; NOFASTLZCNT-NEXT: testl %ecx, %ecx
|
||||
; NOFASTLZCNT-NEXT: sete %cl
|
||||
; NOFASTLZCNT-NEXT: orb %dl, %cl
|
||||
; NOFASTLZCNT-NEXT: orb %al, %cl
|
||||
; NOFASTLZCNT-NEXT: movzbl %cl, %eax
|
||||
; NOFASTLZCNT-NEXT: retq
|
||||
entry:
|
||||
%cmp = icmp eq i32 %a, 0
|
||||
%cmp1 = icmp eq i32 %b, 0
|
||||
%or.cond = or i1 %cmp, %cmp1
|
||||
%cmp3 = icmp eq i32 %c, 0
|
||||
%or.cond5 = or i1 %or.cond, %cmp3
|
||||
%cmp4 = icmp eq i32 %d, 0
|
||||
%.cmp4 = or i1 %or.cond5, %cmp4
|
||||
%lor.ext = zext i1 %.cmp4 to i32
|
||||
ret i32 %lor.ext
|
||||
}
|
||||
|
||||
; Test one 32-bit input, one 64-bit input, output is 32-bit.
|
||||
define i32 @test_zext_cmp9(i32 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_zext_cmp9:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: lzcntq %rsi, %rax
|
||||
; CHECK-NEXT: lzcntl %edi, %ecx
|
||||
; CHECK-NEXT: shrl $5, %ecx
|
||||
; CHECK-NEXT: shrl $6, %eax
|
||||
; CHECK-NEXT: orl %ecx, %eax
|
||||
; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill>
|
||||
; CHECK-NEXT: retq
|
||||
;
|
||||
; NOFASTLZCNT-LABEL: test_zext_cmp9:
|
||||
; NOFASTLZCNT: # BB#0: # %entry
|
||||
; NOFASTLZCNT-NEXT: testl %edi, %edi
|
||||
; NOFASTLZCNT-NEXT: sete %al
|
||||
; NOFASTLZCNT-NEXT: testq %rsi, %rsi
|
||||
; NOFASTLZCNT-NEXT: sete %cl
|
||||
; NOFASTLZCNT-NEXT: orb %al, %cl
|
||||
; NOFASTLZCNT-NEXT: movzbl %cl, %eax
|
||||
; NOFASTLZCNT-NEXT: retq
|
||||
entry:
|
||||
%cmp = icmp eq i32 %a, 0
|
||||
%cmp1 = icmp eq i64 %b, 0
|
||||
%0 = or i1 %cmp, %cmp1
|
||||
%lor.ext = zext i1 %0 to i32
|
||||
ret i32 %lor.ext
|
||||
}
|
||||
|
||||
; Test 2 128-bit inputs, output is 32-bit, no transformations expected.
|
||||
define i32 @test_zext_cmp10(i64 %a.coerce0, i64 %a.coerce1, i64 %b.coerce0, i64 %b.coerce1) {
|
||||
; CHECK-LABEL: test_zext_cmp10:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: orq %rsi, %rdi
|
||||
; CHECK-NEXT: sete %al
|
||||
; CHECK-NEXT: orq %rcx, %rdx
|
||||
; CHECK-NEXT: sete %cl
|
||||
; CHECK-NEXT: orb %al, %cl
|
||||
; CHECK-NEXT: movzbl %cl, %eax
|
||||
; CHECK-NEXT: retq
|
||||
;
|
||||
; NOFASTLZCNT-LABEL: test_zext_cmp10:
|
||||
; NOFASTLZCNT: # BB#0: # %entry
|
||||
; NOFASTLZCNT-NEXT: orq %rsi, %rdi
|
||||
; NOFASTLZCNT-NEXT: sete %al
|
||||
; NOFASTLZCNT-NEXT: orq %rcx, %rdx
|
||||
; NOFASTLZCNT-NEXT: sete %cl
|
||||
; NOFASTLZCNT-NEXT: orb %al, %cl
|
||||
; NOFASTLZCNT-NEXT: movzbl %cl, %eax
|
||||
; NOFASTLZCNT-NEXT: retq
|
||||
entry:
|
||||
%a.sroa.2.0.insert.ext = zext i64 %a.coerce1 to i128
|
||||
%a.sroa.2.0.insert.shift = shl nuw i128 %a.sroa.2.0.insert.ext, 64
|
||||
%a.sroa.0.0.insert.ext = zext i64 %a.coerce0 to i128
|
||||
%a.sroa.0.0.insert.insert = or i128 %a.sroa.2.0.insert.shift, %a.sroa.0.0.insert.ext
|
||||
%b.sroa.2.0.insert.ext = zext i64 %b.coerce1 to i128
|
||||
%b.sroa.2.0.insert.shift = shl nuw i128 %b.sroa.2.0.insert.ext, 64
|
||||
%b.sroa.0.0.insert.ext = zext i64 %b.coerce0 to i128
|
||||
%b.sroa.0.0.insert.insert = or i128 %b.sroa.2.0.insert.shift, %b.sroa.0.0.insert.ext
|
||||
%cmp = icmp eq i128 %a.sroa.0.0.insert.insert, 0
|
||||
%cmp3 = icmp eq i128 %b.sroa.0.0.insert.insert, 0
|
||||
%0 = or i1 %cmp, %cmp3
|
||||
%lor.ext = zext i1 %0 to i32
|
||||
ret i32 %lor.ext
|
||||
}
|
||||
Loading…
Reference in New Issue