ARM: stop emitting blx instructions for most calls on MachO.
I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
This commit is contained in:
parent
ecf7d15d49
commit
b5ece527a1
|
@ -1119,7 +1119,6 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
|
|||
case ARMISD::CALL: return "ARMISD::CALL";
|
||||
case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
|
||||
case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
|
||||
case ARMISD::tCALL: return "ARMISD::tCALL";
|
||||
case ARMISD::BRCOND: return "ARMISD::BRCOND";
|
||||
case ARMISD::BR_JT: return "ARMISD::BR_JT";
|
||||
case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
|
||||
|
@ -1916,7 +1915,7 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||
if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
|
||||
CallOpc = ARMISD::CALL_NOLINK;
|
||||
else
|
||||
CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
|
||||
CallOpc = ARMISD::CALL;
|
||||
} else {
|
||||
if (!isDirect && !Subtarget->hasV5TOps())
|
||||
CallOpc = ARMISD::CALL_NOLINK;
|
||||
|
|
|
@ -43,7 +43,6 @@ namespace llvm {
|
|||
CALL, // Function call.
|
||||
CALL_PRED, // Function call that's predicable.
|
||||
CALL_NOLINK, // Function call with branch not branch-and-link.
|
||||
tCALL, // Thumb function call.
|
||||
BRCOND, // Conditional branch.
|
||||
BR_JT, // Jumptable branch.
|
||||
BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
|
||||
|
|
|
@ -15,10 +15,6 @@
|
|||
// Thumb specific DAG Nodes.
|
||||
//
|
||||
|
||||
def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
|
||||
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
|
||||
SDNPVariadic]>;
|
||||
|
||||
def imm_sr_XFORM: SDNodeXForm<imm, [{
|
||||
unsigned Imm = N->getZExtValue();
|
||||
return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), SDLoc(N), MVT::i32);
|
||||
|
@ -468,7 +464,7 @@ let isCall = 1,
|
|||
def tBL : TIx2<0b11110, 0b11, 1,
|
||||
(outs), (ins pred:$p, t_bltarget:$func), IIC_Br,
|
||||
"bl${p}\t$func",
|
||||
[(ARMtcall tglobaladdr:$func)]>,
|
||||
[(ARMcall tglobaladdr:$func)]>,
|
||||
Requires<[IsThumb]>, Sched<[WriteBrL]> {
|
||||
bits<24> func;
|
||||
let Inst{26} = func{23};
|
||||
|
@ -481,8 +477,7 @@ let isCall = 1,
|
|||
// ARMv5T and above, also used for Thumb2
|
||||
def tBLXi : TIx2<0b11110, 0b11, 0,
|
||||
(outs), (ins pred:$p, t_blxtarget:$func), IIC_Br,
|
||||
"blx${p}\t$func",
|
||||
[(ARMcall tglobaladdr:$func)]>,
|
||||
"blx${p}\t$func", []>,
|
||||
Requires<[IsThumb, HasV5T, IsNotMClass]>, Sched<[WriteBrL]> {
|
||||
bits<24> func;
|
||||
let Inst{26} = func{23};
|
||||
|
@ -496,7 +491,7 @@ let isCall = 1,
|
|||
// Also used for Thumb2
|
||||
def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br,
|
||||
"blx${p}\t$func",
|
||||
[(ARMtcall GPR:$func)]>,
|
||||
[(ARMcall GPR:$func)]>,
|
||||
Requires<[IsThumb, HasV5T]>,
|
||||
T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24;
|
||||
bits<4> func;
|
||||
|
@ -1406,11 +1401,9 @@ def : T1Pat<(ARMWrapperJT tjumptable:$dst),
|
|||
(tLEApcrelJT tjumptable:$dst)>;
|
||||
|
||||
// Direct calls
|
||||
def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
|
||||
def : T1Pat<(ARMcall texternalsym:$func), (tBL texternalsym:$func)>,
|
||||
Requires<[IsThumb]>;
|
||||
|
||||
def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
|
||||
Requires<[IsThumb, HasV5T, IsNotMClass]>;
|
||||
|
||||
// Indirect calls to ARM routines
|
||||
def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
|
||||
|
|
|
@ -1,24 +1,17 @@
|
|||
; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
|
||||
; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB2
|
||||
; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
|
||||
; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
|
||||
; rdar://8690640
|
||||
|
||||
define i32* @t(i32* %x) nounwind {
|
||||
entry:
|
||||
; ARM-LABEL: t:
|
||||
; ARM: push
|
||||
; ARM: mov r7, sp
|
||||
; ARM: bl _foo
|
||||
; ARM: bl _foo
|
||||
; ARM: bl _foo
|
||||
; ARM: pop {r7, pc}
|
||||
; CHECK-LABEL: t:
|
||||
; CHECK: push
|
||||
; CHECK: mov r7, sp
|
||||
; CHECK: bl _foo
|
||||
; CHECK: bl _foo
|
||||
; CHECK: bl _foo
|
||||
; CHECK: pop {r7, pc}
|
||||
|
||||
; THUMB2-LABEL: t:
|
||||
; THUMB2: push
|
||||
; THUMB2: mov r7, sp
|
||||
; THUMB2: blx _foo
|
||||
; THUMB2: blx _foo
|
||||
; THUMB2: blx _foo
|
||||
; THUMB2: pop
|
||||
%0 = tail call i32* @foo(i32* %x) nounwind
|
||||
%1 = tail call i32* @foo(i32* %0) nounwind
|
||||
%2 = tail call i32* @foo(i32* %1) nounwind
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
; CHECK: _f
|
||||
; CHECK-NOT: ands
|
||||
; CHECK: cmp
|
||||
; CHECK: blxle _g
|
||||
; CHECK: blle _g
|
||||
|
||||
define i32 @f(i32 %a, i32 %b) nounwind ssp {
|
||||
entry:
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
; CHECK: _f
|
||||
; CHECK: adds
|
||||
; CHECK-NOT: cmp
|
||||
; CHECK: blxeq _h
|
||||
; CHECK: bleq _h
|
||||
|
||||
define i32 @f(i32 %a, i32 %b) nounwind ssp {
|
||||
entry:
|
||||
|
@ -22,7 +22,7 @@ if.end: ; preds = %if.then, %entry
|
|||
; CHECK: _g
|
||||
; CHECK: orrs
|
||||
; CHECK-NOT: cmp
|
||||
; CHECK: blxeq _h
|
||||
; CHECK: bleq _h
|
||||
|
||||
define i32 @g(i32 %a, i32 %b) nounwind ssp {
|
||||
entry:
|
||||
|
|
|
@ -38,9 +38,9 @@ bb:
|
|||
bb1:
|
||||
; CHECK: %bb1
|
||||
; CHECK-NOT: umull
|
||||
; CHECK: blx _Get
|
||||
; CHECK: bl _Get
|
||||
; CHECK: umull
|
||||
; CHECK: blx _foo
|
||||
; CHECK: bl _foo
|
||||
%tmp5 = load i32, i32* %block_size, align 4
|
||||
%tmp6 = load i32, i32* %block_count, align 4
|
||||
%tmp7 = call %struct.FF* @Get() nounwind
|
||||
|
|
|
@ -29,7 +29,7 @@ target triple = "thumbv7-apple-darwin10"
|
|||
@"\01_fnmatch.initial" = external constant %union.__mbstate_t, align 4
|
||||
|
||||
; CHECK: _fnmatch
|
||||
; CHECK: blx _fnmatch1
|
||||
; CHECK: bl _fnmatch1
|
||||
|
||||
define i32 @"\01_fnmatch"(i8* %pattern, i8* %string, i32 %flags) nounwind optsize {
|
||||
entry:
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix CHECK-ARMV7
|
||||
; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-T2
|
||||
; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-T1
|
||||
; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs -mcpu=cortex-m0 | FileCheck %s --check-prefix=CHECK-M0
|
||||
; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs -mcpu=cortex-m0 | FileCheck %s --check-prefix=CHECK-T1
|
||||
; RUN: llc < %s -mtriple=thumbv7--none-eabi -thread-model single -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-BAREMETAL
|
||||
|
||||
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
|
||||
|
@ -29,8 +29,7 @@ entry:
|
|||
; CHECK: ldrex
|
||||
; CHECK: add
|
||||
; CHECK: strex
|
||||
; CHECK-T1: blx ___sync_fetch_and_add_4
|
||||
; CHECK-M0: bl ___sync_fetch_and_add_4
|
||||
; CHECK-T1: bl ___sync_fetch_and_add_4
|
||||
; CHECK-BAREMETAL: add
|
||||
; CHECK-BAREMETAL-NOT: __sync
|
||||
%0 = atomicrmw add i32* %val1, i32 %tmp monotonic
|
||||
|
@ -38,8 +37,7 @@ entry:
|
|||
; CHECK: ldrex
|
||||
; CHECK: sub
|
||||
; CHECK: strex
|
||||
; CHECK-T1: blx ___sync_fetch_and_sub_4
|
||||
; CHECK-M0: bl ___sync_fetch_and_sub_4
|
||||
; CHECK-T1: bl ___sync_fetch_and_sub_4
|
||||
; CHECK-BAREMETAL: sub
|
||||
; CHECK-BAREMETAL-NOT: __sync
|
||||
%1 = atomicrmw sub i32* %val2, i32 30 monotonic
|
||||
|
@ -47,8 +45,7 @@ entry:
|
|||
; CHECK: ldrex
|
||||
; CHECK: add
|
||||
; CHECK: strex
|
||||
; CHECK-T1: blx ___sync_fetch_and_add_4
|
||||
; CHECK-M0: bl ___sync_fetch_and_add_4
|
||||
; CHECK-T1: bl ___sync_fetch_and_add_4
|
||||
; CHECK-BAREMETAL: add
|
||||
; CHECK-BAREMETAL-NOT: __sync
|
||||
%2 = atomicrmw add i32* %val2, i32 1 monotonic
|
||||
|
@ -56,8 +53,7 @@ entry:
|
|||
; CHECK: ldrex
|
||||
; CHECK: sub
|
||||
; CHECK: strex
|
||||
; CHECK-T1: blx ___sync_fetch_and_sub_4
|
||||
; CHECK-M0: bl ___sync_fetch_and_sub_4
|
||||
; CHECK-T1: bl ___sync_fetch_and_sub_4
|
||||
; CHECK-BAREMETAL: sub
|
||||
; CHECK-BAREMETAL-NOT: __sync
|
||||
%3 = atomicrmw sub i32* %val2, i32 1 monotonic
|
||||
|
@ -65,8 +61,7 @@ entry:
|
|||
; CHECK: ldrex
|
||||
; CHECK: and
|
||||
; CHECK: strex
|
||||
; CHECK-T1: blx ___sync_fetch_and_and_4
|
||||
; CHECK-M0: bl ___sync_fetch_and_and_4
|
||||
; CHECK-T1: bl ___sync_fetch_and_and_4
|
||||
; CHECK-BAREMETAL: and
|
||||
; CHECK-BAREMETAL-NOT: __sync
|
||||
%4 = atomicrmw and i32* %andt, i32 4080 monotonic
|
||||
|
@ -74,8 +69,7 @@ entry:
|
|||
; CHECK: ldrex
|
||||
; CHECK: or
|
||||
; CHECK: strex
|
||||
; CHECK-T1: blx ___sync_fetch_and_or_4
|
||||
; CHECK-M0: bl ___sync_fetch_and_or_4
|
||||
; CHECK-T1: bl ___sync_fetch_and_or_4
|
||||
; CHECK-BAREMETAL: or
|
||||
; CHECK-BAREMETAL-NOT: __sync
|
||||
%5 = atomicrmw or i32* %ort, i32 4080 monotonic
|
||||
|
@ -83,8 +77,7 @@ entry:
|
|||
; CHECK: ldrex
|
||||
; CHECK: eor
|
||||
; CHECK: strex
|
||||
; CHECK-T1: blx ___sync_fetch_and_xor_4
|
||||
; CHECK-M0: bl ___sync_fetch_and_xor_4
|
||||
; CHECK-T1: bl ___sync_fetch_and_xor_4
|
||||
; CHECK-BAREMETAL: eor
|
||||
; CHECK-BAREMETAL-NOT: __sync
|
||||
%6 = atomicrmw xor i32* %xort, i32 4080 monotonic
|
||||
|
@ -92,8 +85,7 @@ entry:
|
|||
; CHECK: ldrex
|
||||
; CHECK: cmp
|
||||
; CHECK: strex
|
||||
; CHECK-T1: blx ___sync_fetch_and_min_4
|
||||
; CHECK-M0: bl ___sync_fetch_and_min_4
|
||||
; CHECK-T1: bl ___sync_fetch_and_min_4
|
||||
; CHECK-BAREMETAL: cmp
|
||||
; CHECK-BAREMETAL-NOT: __sync
|
||||
%7 = atomicrmw min i32* %val2, i32 16 monotonic
|
||||
|
@ -102,8 +94,7 @@ entry:
|
|||
; CHECK: ldrex
|
||||
; CHECK: cmp
|
||||
; CHECK: strex
|
||||
; CHECK-T1: blx ___sync_fetch_and_min_4
|
||||
; CHECK-M0: bl ___sync_fetch_and_min_4
|
||||
; CHECK-T1: bl ___sync_fetch_and_min_4
|
||||
; CHECK-BAREMETAL: cmp
|
||||
; CHECK-BAREMETAL-NOT: __sync
|
||||
%8 = atomicrmw min i32* %val2, i32 %neg monotonic
|
||||
|
@ -111,8 +102,7 @@ entry:
|
|||
; CHECK: ldrex
|
||||
; CHECK: cmp
|
||||
; CHECK: strex
|
||||
; CHECK-T1: blx ___sync_fetch_and_max_4
|
||||
; CHECK-M0: bl ___sync_fetch_and_max_4
|
||||
; CHECK-T1: bl ___sync_fetch_and_max_4
|
||||
; CHECK-BAREMETAL: cmp
|
||||
; CHECK-BAREMETAL-NOT: __sync
|
||||
%9 = atomicrmw max i32* %val2, i32 1 monotonic
|
||||
|
@ -120,8 +110,7 @@ entry:
|
|||
; CHECK: ldrex
|
||||
; CHECK: cmp
|
||||
; CHECK: strex
|
||||
; CHECK-T1: blx ___sync_fetch_and_max_4
|
||||
; CHECK-M0: bl ___sync_fetch_and_max_4
|
||||
; CHECK-T1: bl ___sync_fetch_and_max_4
|
||||
; CHECK-BAREMETAL: cmp
|
||||
; CHECK-BAREMETAL-NOT: __sync
|
||||
%10 = atomicrmw max i32* %val2, i32 0 monotonic
|
||||
|
@ -129,8 +118,7 @@ entry:
|
|||
; CHECK: ldrex
|
||||
; CHECK: cmp
|
||||
; CHECK: strex
|
||||
; CHECK-T1: blx ___sync_fetch_and_umin_4
|
||||
; CHECK-M0: bl ___sync_fetch_and_umin_4
|
||||
; CHECK-T1: bl ___sync_fetch_and_umin_4
|
||||
; CHECK-BAREMETAL: cmp
|
||||
; CHECK-BAREMETAL-NOT: __sync
|
||||
%11 = atomicrmw umin i32* %val2, i32 16 monotonic
|
||||
|
@ -139,8 +127,7 @@ entry:
|
|||
; CHECK: ldrex
|
||||
; CHECK: cmp
|
||||
; CHECK: strex
|
||||
; CHECK-T1: blx ___sync_fetch_and_umin_4
|
||||
; CHECK-M0: bl ___sync_fetch_and_umin_4
|
||||
; CHECK-T1: bl ___sync_fetch_and_umin_4
|
||||
; CHECK-BAREMETAL: cmp
|
||||
; CHECK-BAREMETAL-NOT: __sync
|
||||
%12 = atomicrmw umin i32* %val2, i32 %uneg monotonic
|
||||
|
@ -148,8 +135,7 @@ entry:
|
|||
; CHECK: ldrex
|
||||
; CHECK: cmp
|
||||
; CHECK: strex
|
||||
; CHECK-T1: blx ___sync_fetch_and_umax_4
|
||||
; CHECK-M0: bl ___sync_fetch_and_umax_4
|
||||
; CHECK-T1: bl ___sync_fetch_and_umax_4
|
||||
; CHECK-BAREMETAL: cmp
|
||||
; CHECK-BAREMETAL-NOT: __sync
|
||||
%13 = atomicrmw umax i32* %val2, i32 1 monotonic
|
||||
|
@ -157,8 +143,7 @@ entry:
|
|||
; CHECK: ldrex
|
||||
; CHECK: cmp
|
||||
; CHECK: strex
|
||||
; CHECK-T1: blx ___sync_fetch_and_umax_4
|
||||
; CHECK-M0: bl ___sync_fetch_and_umax_4
|
||||
; CHECK-T1: bl ___sync_fetch_and_umax_4
|
||||
; CHECK-BAREMETAL: cmp
|
||||
; CHECK-BAREMETAL-NOT: __sync
|
||||
%14 = atomicrmw umax i32* %val2, i32 0 monotonic
|
||||
|
@ -175,8 +160,7 @@ entry:
|
|||
; CHECK: ldrex
|
||||
; CHECK: cmp
|
||||
; CHECK: strex
|
||||
; CHECK-T1: blx ___sync_fetch_and_umin_2
|
||||
; CHECK-M0: bl ___sync_fetch_and_umin_2
|
||||
; CHECK-T1: bl ___sync_fetch_and_umin_2
|
||||
; CHECK-BAREMETAL: cmp
|
||||
; CHECK-BAREMETAL-NOT: __sync
|
||||
%0 = atomicrmw umin i16* %val, i16 16 monotonic
|
||||
|
@ -185,8 +169,7 @@ entry:
|
|||
; CHECK: ldrex
|
||||
; CHECK: cmp
|
||||
; CHECK: strex
|
||||
; CHECK-T1: blx ___sync_fetch_and_umin_2
|
||||
; CHECK-M0: bl ___sync_fetch_and_umin_2
|
||||
; CHECK-T1: bl ___sync_fetch_and_umin_2
|
||||
; CHECK-BAREMETAL: cmp
|
||||
; CHECK-BAREMETAL-NOT: __sync
|
||||
%1 = atomicrmw umin i16* %val, i16 %uneg monotonic
|
||||
|
@ -194,8 +177,7 @@ entry:
|
|||
; CHECK: ldrex
|
||||
; CHECK: cmp
|
||||
; CHECK: strex
|
||||
; CHECK-T1: blx ___sync_fetch_and_umax_2
|
||||
; CHECK-M0: bl ___sync_fetch_and_umax_2
|
||||
; CHECK-T1: bl ___sync_fetch_and_umax_2
|
||||
; CHECK-BAREMETAL: cmp
|
||||
; CHECK-BAREMETAL-NOT: __sync
|
||||
%2 = atomicrmw umax i16* %val, i16 1 monotonic
|
||||
|
@ -203,8 +185,7 @@ entry:
|
|||
; CHECK: ldrex
|
||||
; CHECK: cmp
|
||||
; CHECK: strex
|
||||
; CHECK-T1: blx ___sync_fetch_and_umax_2
|
||||
; CHECK-M0: bl ___sync_fetch_and_umax_2
|
||||
; CHECK-T1: bl ___sync_fetch_and_umax_2
|
||||
; CHECK-BAREMETAL: cmp
|
||||
; CHECK-BAREMETAL-NOT: __sync
|
||||
%3 = atomicrmw umax i16* %val, i16 0 monotonic
|
||||
|
@ -220,8 +201,7 @@ entry:
|
|||
; CHECK: ldrex
|
||||
; CHECK: cmp
|
||||
; CHECK: strex
|
||||
; CHECK-T1: blx ___sync_fetch_and_umin_1
|
||||
; CHECK-M0: bl ___sync_fetch_and_umin_1
|
||||
; CHECK-T1: bl ___sync_fetch_and_umin_1
|
||||
; CHECK-BAREMETAL: cmp
|
||||
; CHECK-BAREMETAL-NOT: __sync
|
||||
%0 = atomicrmw umin i8* %val, i8 16 monotonic
|
||||
|
@ -229,8 +209,7 @@ entry:
|
|||
; CHECK: ldrex
|
||||
; CHECK: cmp
|
||||
; CHECK: strex
|
||||
; CHECK-T1: blx ___sync_fetch_and_umin_1
|
||||
; CHECK-M0: bl ___sync_fetch_and_umin_1
|
||||
; CHECK-T1: bl ___sync_fetch_and_umin_1
|
||||
; CHECK-BAREMETAL: cmp
|
||||
; CHECK-BAREMETAL-NOT: __sync
|
||||
%uneg = sub i8 0, 1
|
||||
|
@ -239,8 +218,7 @@ entry:
|
|||
; CHECK: ldrex
|
||||
; CHECK: cmp
|
||||
; CHECK: strex
|
||||
; CHECK-T1: blx ___sync_fetch_and_umax_1
|
||||
; CHECK-M0: bl ___sync_fetch_and_umax_1
|
||||
; CHECK-T1: bl ___sync_fetch_and_umax_1
|
||||
; CHECK-BAREMETAL: cmp
|
||||
; CHECK-BAREMETAL-NOT: __sync
|
||||
%2 = atomicrmw umax i8* %val, i8 1 monotonic
|
||||
|
@ -248,8 +226,7 @@ entry:
|
|||
; CHECK: ldrex
|
||||
; CHECK: cmp
|
||||
; CHECK: strex
|
||||
; CHECK-T1: blx ___sync_fetch_and_umax_1
|
||||
; CHECK-M0: bl ___sync_fetch_and_umax_1
|
||||
; CHECK-T1: bl ___sync_fetch_and_umax_1
|
||||
; CHECK-BAREMETAL: cmp
|
||||
; CHECK-BAREMETAL-NOT: __sync
|
||||
%3 = atomicrmw umax i8* %val, i8 0 monotonic
|
||||
|
@ -342,8 +319,8 @@ define i32 @load_load_add_acquire(i32* %mem1, i32* %mem2) nounwind {
|
|||
; CHECK: dmb
|
||||
; CHECK: add r0,
|
||||
|
||||
; CHECK-M0: ___sync_val_compare_and_swap_4
|
||||
; CHECK-M0: ___sync_val_compare_and_swap_4
|
||||
; CHECK-T1: ___sync_val_compare_and_swap_4
|
||||
; CHECK-T1: ___sync_val_compare_and_swap_4
|
||||
|
||||
; CHECK-BAREMETAL: ldr {{r[0-9]}}, [r0]
|
||||
; CHECK-BAREMETAL-NOT: dmb
|
||||
|
@ -364,8 +341,8 @@ define void @store_store_release(i32* %mem1, i32 %val1, i32* %mem2, i32 %val2) {
|
|||
; CHECK: dmb
|
||||
; CHECK: str r3, [r2]
|
||||
|
||||
; CHECK-M0: ___sync_lock_test_and_set
|
||||
; CHECK-M0: ___sync_lock_test_and_set
|
||||
; CHECK-T1: ___sync_lock_test_and_set
|
||||
; CHECK-T1: ___sync_lock_test_and_set
|
||||
|
||||
; CHECK-BAREMETAL-NOT: dmb
|
||||
; CHECK-BAREMTEAL: str r1, [r0]
|
||||
|
@ -385,9 +362,9 @@ define void @load_fence_store_monotonic(i32* %mem1, i32* %mem2) {
|
|||
; CHECK: dmb
|
||||
; CHECK: str [[R0]], [r1]
|
||||
|
||||
; CHECK-M0: ldr [[R0:r[0-9]]], [r0]
|
||||
; CHECK-M0: dmb
|
||||
; CHECK-M0: str [[R0]], [r1]
|
||||
; CHECK-T1: ldr [[R0:r[0-9]]], [{{r[0-9]+}}]
|
||||
; CHECK-T1: {{dmb|bl ___sync_synchronize}}
|
||||
; CHECK-T1: str [[R0]], [{{r[0-9]+}}]
|
||||
|
||||
; CHECK-BAREMETAL: ldr [[R0:r[0-9]]], [r0]
|
||||
; CHECK-BAREMETAL-NOT: dmb
|
||||
|
|
|
@ -87,7 +87,7 @@ entry:
|
|||
; CHECKT2D-NEXT: bne.w _foo
|
||||
; CHECKT2D-NEXT: push
|
||||
; CHECKT2D-NEXT: mov r7, sp
|
||||
; CHECKT2D-NEXT: blx _foo
|
||||
; CHECKT2D-NEXT: bl _foo
|
||||
br i1 undef, label %bb, label %bb1.lr.ph
|
||||
|
||||
bb1.lr.ph:
|
||||
|
@ -150,8 +150,8 @@ declare i32 @c(i32)
|
|||
|
||||
define i32 @t9() nounwind {
|
||||
; CHECKT2D-LABEL: t9:
|
||||
; CHECKT2D: blx __ZN9MutexLockC1Ev
|
||||
; CHECKT2D: blx __ZN9MutexLockD1Ev
|
||||
; CHECKT2D: bl __ZN9MutexLockC1Ev
|
||||
; CHECKT2D: bl __ZN9MutexLockD1Ev
|
||||
; CHECKT2D: b.w ___divsi3
|
||||
%lock = alloca %class.MutexLock, align 1
|
||||
%1 = call %class.MutexLock* @_ZN9MutexLockC1Ev(%class.MutexLock* %lock)
|
||||
|
@ -170,7 +170,7 @@ declare %class.MutexLock* @_ZN9MutexLockD1Ev(%class.MutexLock*) unnamed_addr nou
|
|||
; otherwise the call to floorf is lost.
|
||||
define float @libcall_tc_test2(float* nocapture %a, float %b) {
|
||||
; CHECKT2D-LABEL: libcall_tc_test2:
|
||||
; CHECKT2D: blx _floorf
|
||||
; CHECKT2D: bl _floorf
|
||||
; CHECKT2D: b.w _truncf
|
||||
%1 = load float, float* %a, align 4
|
||||
%call = tail call float @floorf(float %1)
|
||||
|
|
|
@ -30,7 +30,7 @@ for.end: ; preds = %cond.end
|
|||
%call85 = tail call double @exp(double %mul84) nounwind
|
||||
%mul86 = fmul double %conv78, %call85
|
||||
%add88 = fadd double 0.000000e+00, %mul86
|
||||
; CHECK: blx _exp
|
||||
; CHECK: bl _exp
|
||||
%call100 = tail call double @exp(double %mul84) nounwind
|
||||
%mul101 = fmul double undef, %call100
|
||||
%add103 = fadd double %add46, %mul101
|
||||
|
|
|
@ -7,7 +7,7 @@ define i32 @main(i32 %argc, i8** %argv) nounwind {
|
|||
entry:
|
||||
; THUMB: main
|
||||
call void @printArgsNoRet(i32 1, float 0x4000CCCCC0000000, i8 signext 99, double 4.100000e+00)
|
||||
; THUMB: blx _printArgsNoRet
|
||||
; THUMB: bl _printArgsNoRet
|
||||
; THUMB-NOT: ldr
|
||||
; THUMB-NOT: vldr
|
||||
; THUMB-NOT: vmov
|
||||
|
|
|
@ -41,7 +41,7 @@ define float @test_extend32(half* %addr) {
|
|||
define double @test_extend64(half* %addr) {
|
||||
; CHECK-LABEL: test_extend64:
|
||||
|
||||
; CHECK-OLD: blx ___extendhfsf2
|
||||
; CHECK-OLD: bl ___extendhfsf2
|
||||
; CHECK-OLD: vcvt.f64.f32
|
||||
; CHECK-F16: vcvtb.f32.f16
|
||||
; CHECK-F16: vcvt.f64.f32
|
||||
|
@ -54,7 +54,7 @@ define double @test_extend64(half* %addr) {
|
|||
define void @test_trunc32(float %in, half* %addr) {
|
||||
; CHECK-LABEL: test_trunc32:
|
||||
|
||||
; CHECK-OLD: blx ___truncsfhf2
|
||||
; CHECK-OLD: bl ___truncsfhf2
|
||||
; CHECK-F16: vcvtb.f16.f32
|
||||
; CHECK-V8: vcvtb.f16.f32
|
||||
%val16 = fptrunc float %in to half
|
||||
|
@ -65,8 +65,8 @@ define void @test_trunc32(float %in, half* %addr) {
|
|||
define void @test_trunc64(double %in, half* %addr) {
|
||||
; CHECK-LABEL: test_trunc64:
|
||||
|
||||
; CHECK-OLD: blx ___truncdfhf2
|
||||
; CHECK-F16: blx ___truncdfhf2
|
||||
; CHECK-OLD: bl ___truncdfhf2
|
||||
; CHECK-F16: bl ___truncdfhf2
|
||||
; CHECK-V8: vcvtb.f16.f64
|
||||
%val16 = fptrunc double %in to half
|
||||
store half %val16, half* %addr
|
||||
|
|
|
@ -27,7 +27,7 @@ declare i8* @bar(i32, i8*, i8*)
|
|||
; CHECK-NEXT: LBB{{[0-9_]+}}:
|
||||
; CHECK-NEXT: movw r0, #4567
|
||||
; CHECK-NEXT: [[FOOCALL]]:
|
||||
; CHECK-NEXT: blx _foo
|
||||
; CHECK-NEXT: bl _foo
|
||||
;
|
||||
; CHECK-PROB: BB#0:
|
||||
; CHECK-PROB: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}50.00%) BB#2({{[0-9a-fx/= ]+}}25.00%) BB#4({{[0-9a-fx/= ]+}}25.00%)
|
||||
|
|
|
@ -0,0 +1,20 @@
|
|||
; RUN: llc -mtriple=thumbv7-apple-ios -filetype=obj %s -o %t
|
||||
; RUN: llvm-objdump -macho -d %t | FileCheck %s
|
||||
|
||||
; This function just messes up the offsets enough to make the libcall in
|
||||
; test_local_call unencodable with a blx.
|
||||
define void @thing() {
|
||||
ret void
|
||||
}
|
||||
|
||||
define i64 @__udivdi3(i64 %a, i64 %b) {
|
||||
ret i64 %b
|
||||
}
|
||||
|
||||
define i64 @test_local_call(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_local_call:
|
||||
; CHECK: bl ___udivdi3
|
||||
|
||||
%res = udiv i64 %a, %b
|
||||
ret i64 %res
|
||||
}
|
|
@ -18,9 +18,9 @@ entry:
|
|||
; CHECKELF: mov r0, [[SAVEX]]
|
||||
; CHECKT2D-LABEL: test_identity:
|
||||
; CHECKT2D: mov [[SAVEX:r[0-9]+]], r0
|
||||
; CHECKT2D: blx _identity16
|
||||
; CHECKT2D: bl _identity16
|
||||
; CHECKT2D: uxth r0, r0
|
||||
; CHECKT2D: blx _identity32
|
||||
; CHECKT2D: bl _identity32
|
||||
; CHECKT2D: mov r0, [[SAVEX]]
|
||||
%call = tail call i16 @identity16(i16 %x)
|
||||
%b = zext i16 %call to i32
|
||||
|
@ -49,9 +49,9 @@ entry:
|
|||
; This shouldn't be required
|
||||
; CHECKT2D: mov [[SAVEX:r[0-9]+]], r0
|
||||
|
||||
; CHECKT2D: blx _retzext16
|
||||
; CHECKT2D: bl _retzext16
|
||||
; CHECKT2D-NOT: uxth r0, {{r[0-9]+}}
|
||||
; CHECKT2D: blx _identity32
|
||||
; CHECKT2D: bl _identity32
|
||||
|
||||
; This shouldn't be required
|
||||
; CHECKT2D: mov r0, [[SAVEX]]
|
||||
|
@ -72,9 +72,9 @@ entry:
|
|||
; CHECKELF: mov r0, [[SAVEX]]
|
||||
; CHECKT2D-LABEL: test_mismatched_ret:
|
||||
; CHECKT2D: mov [[SAVEX:r[0-9]+]], r0
|
||||
; CHECKT2D: blx _retzext16
|
||||
; CHECKT2D: bl _retzext16
|
||||
; CHECKT2D: sxth r0, {{r[0-9]+}}
|
||||
; CHECKT2D: blx _identity32
|
||||
; CHECKT2D: bl _identity32
|
||||
; CHECKT2D: mov r0, [[SAVEX]]
|
||||
%call = tail call i16 @retzext16(i16 %x)
|
||||
%b = sext i16 %call to i32
|
||||
|
@ -92,9 +92,9 @@ entry:
|
|||
; CHECKELF: b paramzext16
|
||||
; CHECKT2D-LABEL: test_matched_paramext:
|
||||
; CHECKT2D: uxth r0, r0
|
||||
; CHECKT2D: blx _paramzext16
|
||||
; CHECKT2D: bl _paramzext16
|
||||
; CHECKT2D: uxth r0, r0
|
||||
; CHECKT2D: blx _identity32
|
||||
; CHECKT2D: bl _identity32
|
||||
; CHECKT2D: b.w _paramzext16
|
||||
%call = tail call i16 @paramzext16(i16 %x)
|
||||
%b = zext i16 %call to i32
|
||||
|
@ -118,8 +118,8 @@ entry:
|
|||
; CHECKELF: bl identity32
|
||||
; CHECKELF: b paramzext16
|
||||
; CHECKT2D-LABEL: test_matched_paramext2:
|
||||
; CHECKT2D: blx _paramzext16
|
||||
; CHECKT2D: blx _identity32
|
||||
; CHECKT2D: bl _paramzext16
|
||||
; CHECKT2D: bl _identity32
|
||||
; CHECKT2D: b.w _paramzext16
|
||||
%call = tail call i16 @paramzext16(i16 %x)
|
||||
|
||||
|
@ -143,11 +143,11 @@ entry:
|
|||
|
||||
; CHECKT2D-LABEL: test_matched_bothext:
|
||||
; CHECKT2D: uxth r0, r0
|
||||
; CHECKT2D: blx _bothzext16
|
||||
; CHECKT2D: bl _bothzext16
|
||||
; CHECKT2D-NOT: uxth r0, r0
|
||||
|
||||
; FIXME: Tail call should be OK here
|
||||
; CHECKT2D: blx _identity32
|
||||
; CHECKT2D: bl _identity32
|
||||
|
||||
%call = tail call i16 @bothzext16(i16 %x)
|
||||
%b = zext i16 %x to i32
|
||||
|
@ -167,9 +167,9 @@ entry:
|
|||
; CHECKT2D-LABEL: test_mismatched_bothext:
|
||||
; CHECKT2D: mov [[SAVEX:r[0-9]+]], r0
|
||||
; CHECKT2D: uxth r0, {{r[0-9]+}}
|
||||
; CHECKT2D: blx _bothzext16
|
||||
; CHECKT2D: bl _bothzext16
|
||||
; CHECKT2D: sxth r0, [[SAVEX]]
|
||||
; CHECKT2D: blx _identity32
|
||||
; CHECKT2D: bl _identity32
|
||||
; CHECKT2D: mov r0, [[SAVEX]]
|
||||
%call = tail call i16 @bothzext16(i16 %x)
|
||||
%b = sext i16 %x to i32
|
||||
|
|
|
@ -74,7 +74,7 @@ declare void @terminatev()
|
|||
; %do.body.i.i.i.
|
||||
|
||||
; CHECK-LABEL: __Z4foo1c:
|
||||
; CHECK: blx __Znwm
|
||||
; CHECK: bl __Znwm
|
||||
; CHECK: {{.*}}@ %do.body.i.i.i.preheader
|
||||
; CHECK: str r0, [sp, [[OFFSET:#[0-9]+]]]
|
||||
; CHECK: {{.*}}@ %do.body.i.i.i
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
; RUN: llc < %s -mtriple=armv7-apple-ios6.0 | FileCheck %s
|
||||
; RUN: llc < %s -mtriple=thumbv7-apple-ios6.0 | FileCheck %s -check-prefix=THUMB
|
||||
; RUN: llc < %s -mtriple=thumbv7-apple-ios6.0 | FileCheck %s
|
||||
; RUN: llc < %s -mtriple=armv7-unknown-nacl-gnueabi | FileCheck %s -check-prefix=NACL
|
||||
; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi | FileCheck %s -check-prefix=NOMOVT
|
||||
|
||||
|
@ -15,10 +15,6 @@ entry:
|
|||
; CHECK: ldr
|
||||
; CHECK: str
|
||||
; CHECK-NOT:bne
|
||||
; THUMB-LABEL: f:
|
||||
; THUMB: ldr
|
||||
; THUMB: str
|
||||
; THUMB-NOT:bne
|
||||
%st = alloca %struct.SmallStruct, align 4
|
||||
%call = call i32 @e1(%struct.SmallStruct* byval %st)
|
||||
ret i32 0
|
||||
|
@ -32,11 +28,6 @@ entry:
|
|||
; CHECK: sub
|
||||
; CHECK: str
|
||||
; CHECK: bne
|
||||
; THUMB-LABEL: g:
|
||||
; THUMB: ldr
|
||||
; THUMB: sub
|
||||
; THUMB: str
|
||||
; THUMB: bne
|
||||
; NACL-LABEL: g:
|
||||
; Ensure that use movw instead of constpool for the loop trip count. But don't
|
||||
; match the __stack_chk_guard movw
|
||||
|
@ -58,11 +49,6 @@ entry:
|
|||
; CHECK: sub
|
||||
; CHECK: vst1
|
||||
; CHECK: bne
|
||||
; THUMB-LABEL: h:
|
||||
; THUMB: vld1
|
||||
; THUMB: sub
|
||||
; THUMB: vst1
|
||||
; THUMB: bne
|
||||
; NACL: movw r{{[1-9]}}, #
|
||||
; NACL: vld1
|
||||
; NACL: sub
|
||||
|
@ -83,8 +69,6 @@ declare i32 @e3(%struct.LargeStruct* nocapture byval align 16 %in) nounwind
|
|||
define void @f3(%struct.SmallStruct* nocapture byval %s) nounwind optsize {
|
||||
; CHECK-LABEL: f3
|
||||
; CHECK: bl _consumestruct
|
||||
; THUMB-LABEL: f3
|
||||
; THUMB: blx _consumestruct
|
||||
entry:
|
||||
%0 = bitcast %struct.SmallStruct* %s to i8*
|
||||
tail call void @consumestruct(i8* %0, i32 80) optsize
|
||||
|
@ -94,8 +78,6 @@ entry:
|
|||
define void @f4(%struct.SmallStruct* nocapture byval %s) nounwind optsize {
|
||||
; CHECK-LABEL: f4
|
||||
; CHECK: bl _consumestruct
|
||||
; THUMB-LABEL: f4
|
||||
; THUMB: blx _consumestruct
|
||||
entry:
|
||||
%addr = getelementptr inbounds %struct.SmallStruct, %struct.SmallStruct* %s, i32 0, i32 0
|
||||
%0 = bitcast i32* %addr to i8*
|
||||
|
@ -106,9 +88,7 @@ entry:
|
|||
; We can do tail call here since s is in the incoming argument area.
|
||||
define void @f5(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture byval %s) nounwind optsize {
|
||||
; CHECK-LABEL: f5
|
||||
; CHECK: b _consumestruct
|
||||
; THUMB-LABEL: f5
|
||||
; THUMB: b.w _consumestruct
|
||||
; CHECK: b{{(\.w)?}} _consumestruct
|
||||
entry:
|
||||
%0 = bitcast %struct.SmallStruct* %s to i8*
|
||||
tail call void @consumestruct(i8* %0, i32 80) optsize
|
||||
|
@ -117,9 +97,7 @@ entry:
|
|||
|
||||
define void @f6(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture byval %s) nounwind optsize {
|
||||
; CHECK-LABEL: f6
|
||||
; CHECK: b _consumestruct
|
||||
; THUMB-LABEL: f6
|
||||
; THUMB: b.w _consumestruct
|
||||
; CHECK: b{{(\.w)?}} _consumestruct
|
||||
entry:
|
||||
%addr = getelementptr inbounds %struct.SmallStruct, %struct.SmallStruct* %s, i32 0, i32 0
|
||||
%0 = bitcast i32* %addr to i8*
|
||||
|
@ -137,9 +115,6 @@ define void @test_I_16() {
|
|||
; CHECK-LABEL: test_I_16
|
||||
; CHECK: ldrb
|
||||
; CHECK: strb
|
||||
; THUMB-LABEL: test_I_16
|
||||
; THUMB: ldrb
|
||||
; THUMB: strb
|
||||
entry:
|
||||
call void @use_I(%struct.I.8* byval align 16 undef)
|
||||
ret void
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
; RUN: llc -mtriple thumbv7-windows-coff -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-COFF
|
||||
; RUN: llc -mtriple thumbv7-elf -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-ELF
|
||||
; RUN: llc -mtriple thumbv7-macho -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-MACHO
|
||||
; RUN: llc -mtriple thumbv7-elf -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-OTHER
|
||||
; RUN: llc -mtriple thumbv7-macho -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-OTHER
|
||||
|
||||
declare i8* @f()
|
||||
declare extern_weak i8* @g(i8*)
|
||||
|
@ -14,6 +14,5 @@ define void @test() {
|
|||
}
|
||||
|
||||
; CHECK-COFF: b g
|
||||
; CHECK-ELF: bl g
|
||||
; CHECK-MACHO: blx _g
|
||||
; CHECK-OTHER: bl {{_?}}g
|
||||
|
||||
|
|
|
@ -24,7 +24,7 @@ entry:
|
|||
; CHECKELF: b B_ctor_base
|
||||
; CHECKT2D-LABEL: C_ctor_base:
|
||||
; CHECKT2D-NOT: mov {{r[0-9]+}}, r0
|
||||
; CHECKT2D: blx _A_ctor_base
|
||||
; CHECKT2D: bl _A_ctor_base
|
||||
; CHECKT2D-NOT: mov r0, {{r[0-9]+}}
|
||||
; CHECKT2D: b.w _B_ctor_base
|
||||
%0 = bitcast %struct.C* %this to %struct.A*
|
||||
|
@ -43,7 +43,7 @@ entry:
|
|||
; CHECKELF-NOT: b B_ctor_base_nothisret
|
||||
; CHECKT2D-LABEL: C_ctor_base_nothisret:
|
||||
; CHECKT2D: mov [[SAVETHIS:r[0-9]+]], r0
|
||||
; CHECKT2D: blx _A_ctor_base_nothisret
|
||||
; CHECKT2D: bl _A_ctor_base_nothisret
|
||||
; CHECKT2D: mov r0, [[SAVETHIS]]
|
||||
; CHECKT2D-NOT: b.w _B_ctor_base_nothisret
|
||||
%0 = bitcast %struct.C* %this to %struct.A*
|
||||
|
@ -82,7 +82,7 @@ entry:
|
|||
; CHECKELF: b B_ctor_complete
|
||||
; CHECKT2D-LABEL: D_ctor_base:
|
||||
; CHECKT2D-NOT: mov {{r[0-9]+}}, r0
|
||||
; CHECKT2D: blx _B_ctor_complete
|
||||
; CHECKT2D: bl _B_ctor_complete
|
||||
; CHECKT2D-NOT: mov r0, {{r[0-9]+}}
|
||||
; CHECKT2D: b.w _B_ctor_complete
|
||||
%b = getelementptr inbounds %struct.D, %struct.D* %this, i32 0, i32 0
|
||||
|
|
|
@ -52,7 +52,7 @@ define void @test_simple_var() {
|
|||
|
||||
; CHECK: mov r0, sp
|
||||
; CHECK-NOT: adds r0
|
||||
; CHECK: blx
|
||||
; CHECK: bl
|
||||
call void @take_ptr(i8* %addr8)
|
||||
ret void
|
||||
}
|
||||
|
@ -67,12 +67,12 @@ define void @test_local_var_addr_aligned() {
|
|||
%addr2 = bitcast i32* %addr2.32 to i8*
|
||||
|
||||
; CHECK: add r0, sp, #{{[0-9]+}}
|
||||
; CHECK: blx
|
||||
; CHECK: bl
|
||||
call void @take_ptr(i8* %addr1)
|
||||
|
||||
; CHECK: mov r0, sp
|
||||
; CHECK-NOT: add r0
|
||||
; CHECK: blx
|
||||
; CHECK: bl
|
||||
call void @take_ptr(i8* %addr2)
|
||||
|
||||
ret void
|
||||
|
@ -87,7 +87,7 @@ define void @test_local_var_big_offset() {
|
|||
|
||||
; CHECK: add [[RTMP:r[0-9]+]], sp, #1020
|
||||
; CHECK: adds [[RTMP]], #8
|
||||
; CHECK: blx
|
||||
; CHECK: bl
|
||||
call void @take_ptr(i8* %addr1)
|
||||
|
||||
ret void
|
||||
|
@ -100,7 +100,7 @@ define void @test_local_var_offset_1020() {
|
|||
%addr2 = alloca i8, i32 1020
|
||||
|
||||
; CHECK: add r0, sp, #1020
|
||||
; CHECK-NEXT: blx
|
||||
; CHECK-NEXT: bl
|
||||
call void @take_ptr(i8* %addr1)
|
||||
|
||||
ret void
|
||||
|
@ -116,7 +116,7 @@ define void @test_local_var_offset_1268() {
|
|||
|
||||
; CHECK: add r0, sp, #1020
|
||||
; CHECK: adds r0, #248
|
||||
; CHECK-NEXT: blx
|
||||
; CHECK-NEXT: bl
|
||||
call void @take_ptr(i8* %addr1)
|
||||
|
||||
ret void
|
||||
|
|
|
@ -5,7 +5,7 @@ declare double @cos(double) nounwind readnone
|
|||
|
||||
define double @test_stret(double %in) {
|
||||
; CHECK-LABEL: test_stret:
|
||||
; CHECK: blx ___sincos_stret
|
||||
; CHECK: bl ___sincos_stret
|
||||
; CHECK-NOT: ldr
|
||||
; CHECK: vadd.f64 d0, d0, d1
|
||||
|
||||
|
|
|
@ -4,7 +4,7 @@
|
|||
|
||||
define float @test_call(float %a, float %b) {
|
||||
; CHECK-HARD: vadd.f32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
|
||||
; CHECK-SOFTISH: blx ___addsf3vfp
|
||||
; CHECK-SOFTISH: bl ___addsf3vfp
|
||||
; CHECK-SOFT: bl ___addsf3{{$}}
|
||||
%sum = fadd float %a, %b
|
||||
ret float %sum
|
||||
|
|
|
@ -8,10 +8,10 @@
|
|||
@llvm.used = appending global [1 x i8*] [i8* bitcast (void (%0*, i32, i32)* @_Z19getClosestDiagonal3ii to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
|
||||
|
||||
define void @_Z19getClosestDiagonal3ii(%0* noalias sret, i32, i32) nounwind {
|
||||
; CHECK: blx ___muldf3
|
||||
; CHECK: blx ___muldf3
|
||||
; CHECK: bl ___muldf3
|
||||
; CHECK: bl ___muldf3
|
||||
; CHECK: beq LBB0
|
||||
; CHECK: blx ___muldf3
|
||||
; CHECK: bl ___muldf3
|
||||
; <label>:3
|
||||
switch i32 %1, label %4 [
|
||||
i32 0, label %5
|
||||
|
|
|
@ -4,7 +4,7 @@
|
|||
|
||||
define void @t1() {
|
||||
; V6-LABEL: t1:
|
||||
; V6: blx {{_*}}sync_synchronize
|
||||
; V6: bl {{_*}}sync_synchronize
|
||||
|
||||
; V6M-LABEL: t1:
|
||||
; V6M: dmb sy
|
||||
|
|
|
@ -31,9 +31,9 @@ return: ; preds = %bb, %entry
|
|||
|
||||
define i32 @test_dead_cycle(i32 %n) nounwind {
|
||||
; CHECK-LABEL: test_dead_cycle:
|
||||
; CHECK: blx
|
||||
; CHECK: bl
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blx
|
||||
; CHECK: bl
|
||||
entry:
|
||||
%0 = icmp eq i32 %n, 1 ; <i1> [#uses=1]
|
||||
br i1 %0, label %return, label %bb.nph
|
||||
|
|
|
@ -14,7 +14,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-
|
|||
%s5 = type { i32 }
|
||||
|
||||
; Make sure the cmp is not scheduled before the InlineAsm that clobbers cc.
|
||||
; CHECK: blx _f2
|
||||
; CHECK: bl _f2
|
||||
; CHECK: cmp r0, #0
|
||||
; CHECK-NOT: cmp
|
||||
; CHECK: InlineAsm Start
|
||||
|
|
|
@ -1,26 +1,20 @@
|
|||
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s -check-prefix=DARWIN
|
||||
; RUN: llc < %s -mtriple=thumbv7-linux -mattr=+thumb2 | FileCheck %s -check-prefix=LINUX
|
||||
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s
|
||||
; RUN: llc < %s -mtriple=thumbv7-linux -mattr=+thumb2 | FileCheck %s
|
||||
|
||||
@t = weak global i32 ()* null ; <i32 ()**> [#uses=1]
|
||||
|
||||
declare void @g(i32, i32, i32, i32)
|
||||
|
||||
define void @f() {
|
||||
; DARWIN-LABEL: f:
|
||||
; DARWIN: blx _g
|
||||
|
||||
; LINUX-LABEL: f:
|
||||
; LINUX: bl g
|
||||
; CHECK-LABEL: f:
|
||||
; CHECK: bl {{_?}}g
|
||||
call void @g( i32 1, i32 2, i32 3, i32 4 )
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @h() {
|
||||
; DARWIN-LABEL: h:
|
||||
; DARWIN: blx r0
|
||||
|
||||
; LINUX-LABEL: h:
|
||||
; LINUX: blx r0
|
||||
; CHECK-LABEL: h:
|
||||
; CHECK: blx r0
|
||||
%tmp = load i32 ()*, i32 ()** @t ; <i32 ()*> [#uses=1]
|
||||
%tmp.upgrd.2 = call i32 %tmp( ) ; <i32> [#uses=0]
|
||||
ret void
|
||||
|
|
|
@ -49,9 +49,9 @@ define i32 @t3() {
|
|||
define void @t4(i32 %a0, i32 %a1, i32 %a2) {
|
||||
; ALL-LABEL: t4:
|
||||
; ALL: stm.w sp, {r0, r1, r2}
|
||||
; ALL: blx _ext
|
||||
; ALL: bl _ext
|
||||
; ALL: ldm.w sp, {r0, r1, r2}
|
||||
; ALL: blx _f2
|
||||
; ALL: bl _f2
|
||||
%arr = alloca [4 x i32], align 4
|
||||
%p0 = getelementptr inbounds [4 x i32], [4 x i32]* %arr, i64 0, i64 0
|
||||
%p1 = getelementptr inbounds [4 x i32], [4 x i32]* %arr, i64 0, i64 1
|
||||
|
|
Loading…
Reference in New Issue