parent
e18aaf2c4b
commit
b59f7734b9
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@ -3135,16 +3135,16 @@ def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
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//
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let Defs = [EFLAGS] in {
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let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
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def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
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def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
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"test{b}\t{$src2, $src1|$src1, $src2}",
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[(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
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(implicit EFLAGS)]>;
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def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
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def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
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"test{w}\t{$src2, $src1|$src1, $src2}",
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[(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
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(implicit EFLAGS)]>,
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OpSize;
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def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
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def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
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"test{l}\t{$src2, $src1|$src1, $src2}",
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[(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
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(implicit EFLAGS)]>;
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@ -38,4 +38,6 @@ rdtscp
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movl %eax, 16(%ebp)
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// CHECK: movl %eax, -16(%ebp) # encoding: [0x89,0x45,0xf0]
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movl %eax, -16(%ebp)
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// CHECK: testb %bl, %cl # encoding: [0x84,0xcb]
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testb %bl, %cl
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