[mips] [IAS] Give expandLoadAddressSym() more specific arguments. NFC.
Summary: If we only pass the necessary operands, we don't have to determine the position of the symbol operand when entering expandLoadAddressSym(). This simplifies the expandLoadAddressSym() code. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9291 llvm-svn: 237355
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@ -194,8 +194,8 @@ class MipsAsmParser : public MCTargetAsmParser {
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bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc,
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bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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SmallVectorImpl<MCInst> &Instructions);
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void expandLoadAddressSym(MCInst &Inst, SMLoc IDLoc,
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void expandLoadAddressSym(const MCOperand &DstRegOp, const MCOperand &SymOp,
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SmallVectorImpl<MCInst> &Instructions);
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SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions);
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void expandMemInst(MCInst &Inst, SMLoc IDLoc,
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void expandMemInst(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions, bool isLoad,
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SmallVectorImpl<MCInst> &Instructions, bool isLoad,
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@ -1869,17 +1869,18 @@ bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
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bool
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bool
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MipsAsmParser::expandLoadAddressReg(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
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MipsAsmParser::expandLoadAddressReg(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions) {
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SmallVectorImpl<MCInst> &Instructions) {
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const MCOperand &DstRegOp = Inst.getOperand(0);
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assert(DstRegOp.isReg() && "expected register operand kind");
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const MCOperand &ImmOp = Inst.getOperand(2);
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const MCOperand &ImmOp = Inst.getOperand(2);
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assert((ImmOp.isImm() || ImmOp.isExpr()) &&
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assert((ImmOp.isImm() || ImmOp.isExpr()) &&
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"expected immediate operand kind");
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"expected immediate operand kind");
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if (!ImmOp.isImm()) {
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if (!ImmOp.isImm()) {
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expandLoadAddressSym(Inst, IDLoc, Instructions);
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expandLoadAddressSym(DstRegOp, ImmOp, IDLoc, Instructions);
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return false;
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return false;
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}
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}
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const MCOperand &SrcRegOp = Inst.getOperand(1);
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const MCOperand &SrcRegOp = Inst.getOperand(1);
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assert(SrcRegOp.isReg() && "expected register operand kind");
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assert(SrcRegOp.isReg() && "expected register operand kind");
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const MCOperand &DstRegOp = Inst.getOperand(0);
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assert(DstRegOp.isReg() && "expected register operand kind");
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if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), SrcRegOp.getReg(),
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if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), SrcRegOp.getReg(),
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Is32BitImm, IDLoc, Instructions))
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Is32BitImm, IDLoc, Instructions))
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@ -1891,15 +1892,16 @@ MipsAsmParser::expandLoadAddressReg(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
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bool
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bool
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MipsAsmParser::expandLoadAddressImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
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MipsAsmParser::expandLoadAddressImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions) {
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SmallVectorImpl<MCInst> &Instructions) {
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const MCOperand &DstRegOp = Inst.getOperand(0);
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assert(DstRegOp.isReg() && "expected register operand kind");
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const MCOperand &ImmOp = Inst.getOperand(1);
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const MCOperand &ImmOp = Inst.getOperand(1);
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assert((ImmOp.isImm() || ImmOp.isExpr()) &&
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assert((ImmOp.isImm() || ImmOp.isExpr()) &&
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"expected immediate operand kind");
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"expected immediate operand kind");
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if (!ImmOp.isImm()) {
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if (!ImmOp.isImm()) {
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expandLoadAddressSym(Inst, IDLoc, Instructions);
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expandLoadAddressSym(DstRegOp, ImmOp, IDLoc, Instructions);
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return false;
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return false;
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}
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}
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const MCOperand &DstRegOp = Inst.getOperand(0);
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assert(DstRegOp.isReg() && "expected register operand kind");
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if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,
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if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,
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Is32BitImm, IDLoc, Instructions))
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Is32BitImm, IDLoc, Instructions))
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@ -1909,23 +1911,11 @@ MipsAsmParser::expandLoadAddressImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
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}
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}
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void
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void
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MipsAsmParser::expandLoadAddressSym(MCInst &Inst, SMLoc IDLoc,
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MipsAsmParser::expandLoadAddressSym(const MCOperand &DstRegOp,
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const MCOperand &SymOp, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions) {
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SmallVectorImpl<MCInst> &Instructions) {
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// FIXME: If we do have a valid at register to use, we should generate a
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// slightly shorter sequence here.
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MCInst tmpInst;
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MCInst tmpInst;
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int ExprOperandNo = 1;
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unsigned RegNo = DstRegOp.getReg();
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// Sometimes the assembly parser will get the immediate expression as
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// a $zero + an immediate.
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if (Inst.getNumOperands() == 3) {
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assert(Inst.getOperand(1).getReg() ==
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(isGP64bit() ? Mips::ZERO_64 : Mips::ZERO));
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ExprOperandNo = 2;
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}
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const MCOperand &SymOp = Inst.getOperand(ExprOperandNo);
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assert(SymOp.isExpr() && "expected symbol operand kind");
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const MCOperand &RegOp = Inst.getOperand(0);
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unsigned RegNo = RegOp.getReg();
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const MCSymbolRefExpr *Symbol = cast<MCSymbolRefExpr>(SymOp.getExpr());
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const MCSymbolRefExpr *Symbol = cast<MCSymbolRefExpr>(SymOp.getExpr());
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const MCSymbolRefExpr *HiExpr =
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const MCSymbolRefExpr *HiExpr =
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MCSymbolRefExpr::Create(Symbol->getSymbol().getName(),
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MCSymbolRefExpr::Create(Symbol->getSymbol().getName(),
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