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add support for the prefetch/prefetchw instructions, move femms into 

the right file.  The assembler supports all the 3dnow instructions now,
but not the "3dnowa" ones.

llvm-svn: 115468
This commit is contained in:
Chris Lattner 2010-10-03 18:42:30 +00:00
parent 3a0a620c2e
commit b44b202d66
3 changed files with 30 additions and 13 deletions
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31
llvm/lib/Target/X86/X86Instr3DNow.td
View File

@ -16,9 +16,14 @@
class I3DNow<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern>
: I<o, F, outs, ins, asm, pattern>, TB, Requires<[Has3DNow]>,
Has3DNow0F0FOpcode {
// FIXME: The disassembler doesn't support 3DNow! yet.
: I<o, F, outs, ins, asm, pattern>, TB, Requires<[Has3DNow]> {
}
class I3DNow_binop<bits<8> o, Format F, dag ins, string Mnemonic>
: I<o, F, (outs VR64:$dst), ins,
!strconcat(Mnemonic, "\t{$src2, $dst|$dst, $src2}"), []>,
TB, Requires<[Has3DNow]>, Has3DNow0F0FOpcode {
// FIXME: The disassembler doesn't support Has3DNow0F0FOpcode yet.
let isAsmParserOnly = 1;
}
@ -26,13 +31,9 @@ class I3DNow<bits<8> o, Format F, dag outs, dag ins, string asm,
let Constraints = "$src1 = $dst" in {
// MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic.
// When this is cleaned up, remove the FIXME from X86RecognizableInstr.cpp.
multiclass I3DNow_binop_rm<bits<8> opc, string Mnemonic> {
def rr : I3DNow<opc, MRMSrcReg, (outs VR64:$dst),
(ins VR64:$src1, VR64:$src2),
!strconcat(Mnemonic, "\t{$src2, $dst|$dst, $src2}"), []>;
def rm : I3DNow<opc, MRMSrcMem, (outs VR64:$dst),
(ins VR64:$src1, i64mem:$src2),
!strconcat(Mnemonic, "\t{$src2, $dst|$dst, $src2}"), []>;
multiclass I3DNow_binop_rm<bits<8> opc, string Mn> {
def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn>;
def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn>;
}
}
@ -57,6 +58,16 @@ defm PI2FD : I3DNow_binop_rm<0x0D, "pi2fd">;
defm PMULHRW : I3DNow_binop_rm<0xB7, "pmulhrw">;
def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]>;
def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i32mem:$addr),
"prefetch $addr", []>;
// FIXME: Diassembler gets a bogus decode conflict.
let isAsmParserOnly = 1 in {
def PREFETCHW : I3DNow<0x0D, MRM1m, (outs), (ins i16mem:$addr),
"prefetchw $addr", []>;
}
// TODO: Add support for the "3DNowA" instructions.

4
llvm/lib/Target/X86/X86InstrMMX.td
View File

@ -121,13 +121,11 @@ multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
}
//===----------------------------------------------------------------------===//
// MMX EMMS & FEMMS Instructions
// MMX EMMS Instruction
//===----------------------------------------------------------------------===//
def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms",
[(int_x86_mmx_emms)]>;
def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms",
[(int_x86_mmx_femms)]>;
//===----------------------------------------------------------------------===//
// MMX Scalar Instructions

8
llvm/test/MC/X86/3DNow.s
View File

@ -66,3 +66,11 @@ pi2fd %mm2, %mm1
// CHECK: pmulhrw %mm2, %mm1 # encoding: [0x0f,0x0f,0xca,0xb7]
pmulhrw %mm2, %mm1
// CHECK: femms # encoding: [0x0f,0x0e]
femms
// CHECK: prefetch (%rax) # encoding: [0x0f,0x0d,0x00]
// CHECK: prefetchw (%rax) # encoding: [0x0f,0x0d,0x08]
prefetch (%rax)
prefetchw (%rax)