[InstCombine][AVX-512] Teach InstCombineCalls to handle the new unmasked AVX-512 variable shift intrinsics.
llvm-svn: 286755
This commit is contained in:
Craig Topper
parent
43e97649a1
commit
b4173a5a70
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@ -258,8 +258,7 @@ static Value *simplifyX86immShift(const IntrinsicInst &II,
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bool ShiftLeft = false;
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switch (II.getIntrinsicID()) {
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default:
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return nullptr;
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default: llvm_unreachable("Unexpected intrinsic!");
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case Intrinsic::x86_sse2_psra_d:
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case Intrinsic::x86_sse2_psra_w:
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case Intrinsic::x86_sse2_psrai_d:
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@ -393,10 +392,13 @@ static Value *simplifyX86varShift(const IntrinsicInst &II,
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bool ShiftLeft = false;
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switch (II.getIntrinsicID()) {
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default:
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return nullptr;
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default: llvm_unreachable("Unexpected intrinsic!");
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case Intrinsic::x86_avx2_psrav_d:
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case Intrinsic::x86_avx2_psrav_d_256:
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case Intrinsic::x86_avx512_psrav_q_128:
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case Intrinsic::x86_avx512_psrav_q_256:
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case Intrinsic::x86_avx512_psrav_d_512:
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case Intrinsic::x86_avx512_psrav_q_512:
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LogicalShift = false;
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ShiftLeft = false;
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break;
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@ -404,6 +406,8 @@ static Value *simplifyX86varShift(const IntrinsicInst &II,
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case Intrinsic::x86_avx2_psrlv_d_256:
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case Intrinsic::x86_avx2_psrlv_q:
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case Intrinsic::x86_avx2_psrlv_q_256:
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case Intrinsic::x86_avx512_psrlv_d_512:
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case Intrinsic::x86_avx512_psrlv_q_512:
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LogicalShift = true;
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ShiftLeft = false;
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break;
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@ -411,6 +415,8 @@ static Value *simplifyX86varShift(const IntrinsicInst &II,
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case Intrinsic::x86_avx2_psllv_d_256:
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case Intrinsic::x86_avx2_psllv_q:
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case Intrinsic::x86_avx2_psllv_q_256:
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case Intrinsic::x86_avx512_psllv_d_512:
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case Intrinsic::x86_avx512_psllv_q_512:
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LogicalShift = true;
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ShiftLeft = true;
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break;
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@ -1873,12 +1879,20 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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case Intrinsic::x86_avx2_psllv_d_256:
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case Intrinsic::x86_avx2_psllv_q:
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case Intrinsic::x86_avx2_psllv_q_256:
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case Intrinsic::x86_avx512_psllv_d_512:
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case Intrinsic::x86_avx512_psllv_q_512:
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case Intrinsic::x86_avx2_psrav_d:
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case Intrinsic::x86_avx2_psrav_d_256:
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case Intrinsic::x86_avx512_psrav_q_128:
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case Intrinsic::x86_avx512_psrav_q_256:
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case Intrinsic::x86_avx512_psrav_d_512:
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case Intrinsic::x86_avx512_psrav_q_512:
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case Intrinsic::x86_avx2_psrlv_d:
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case Intrinsic::x86_avx2_psrlv_d_256:
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case Intrinsic::x86_avx2_psrlv_q:
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case Intrinsic::x86_avx2_psrlv_q_256:
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case Intrinsic::x86_avx512_psrlv_d_512:
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case Intrinsic::x86_avx512_psrlv_q_512:
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if (Value *V = simplifyX86varShift(*II, *Builder))
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return replaceInstUsesWith(*II, V);
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break;
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@ -1564,6 +1564,14 @@ define <8 x i32> @avx2_psrav_d_256_0(<8 x i32> %v) {
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ret <8 x i32> %1
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}
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define <16 x i32> @avx512_psrav_d_512_0(<16 x i32> %v) {
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; CHECK-LABEL: @avx512_psrav_d_512_0(
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; CHECK-NEXT: ret <16 x i32> %v
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;
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%1 = tail call <16 x i32> @llvm.x86.avx512.psrav.d.512(<16 x i32> %v, <16 x i32> zeroinitializer)
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ret <16 x i32> %1
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}
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define <4 x i32> @avx2_psrav_d_128_var(<4 x i32> %v) {
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; CHECK-LABEL: @avx2_psrav_d_128_var(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i32> %v, <i32 0, i32 8, i32 16, i32 31>
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@ -1582,6 +1590,15 @@ define <8 x i32> @avx2_psrav_d_256_var(<8 x i32> %v) {
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ret <8 x i32> %1
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}
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define <16 x i32> @avx512_psrav_d_512_var(<16 x i32> %v) {
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; CHECK-LABEL: @avx512_psrav_d_512_var(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <16 x i32> %v, <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>
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; CHECK-NEXT: ret <16 x i32> [[TMP1]]
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;
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%1 = tail call <16 x i32> @llvm.x86.avx512.psrav.d.512(<16 x i32> %v, <16 x i32> <i32 0, i32 8, i32 16, i32 24, i32 32, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 24, i32 32, i32 24, i32 8, i32 0>)
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ret <16 x i32> %1
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}
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define <4 x i32> @avx2_psrav_d_128_allbig(<4 x i32> %v) {
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; CHECK-LABEL: @avx2_psrav_d_128_allbig(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i32> %v, <i32 31, i32 31, i32 31, i32 undef>
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@ -1600,6 +1617,15 @@ define <8 x i32> @avx2_psrav_d_256_allbig(<8 x i32> %v) {
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ret <8 x i32> %1
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}
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define <16 x i32> @avx512_psrav_d_512_allbig(<16 x i32> %v) {
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; CHECK-LABEL: @avx512_psrav_d_512_allbig(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <16 x i32> %v, <i32 undef, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 undef, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
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; CHECK-NEXT: ret <16 x i32> [[TMP1]]
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;
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%1 = tail call <16 x i32> @llvm.x86.avx512.psrav.d.512(<16 x i32> %v, <16 x i32> <i32 undef, i32 100, i32 255, i32 55555, i32 -32, i32 -100, i32 -255, i32 -55555, i32 undef, i32 100, i32 255, i32 55555, i32 -32, i32 -100, i32 -255, i32 -55555>)
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ret <16 x i32> %1
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}
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define <4 x i32> @avx2_psrav_d_128_undef(<4 x i32> %v) {
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; CHECK-LABEL: @avx2_psrav_d_128_undef(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i32> %v, <i32 undef, i32 8, i32 16, i32 31>
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@ -1620,6 +1646,122 @@ define <8 x i32> @avx2_psrav_d_256_undef(<8 x i32> %v) {
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ret <8 x i32> %2
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}
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define <16 x i32> @avx512_psrav_d_512_undef(<16 x i32> %v) {
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; CHECK-LABEL: @avx512_psrav_d_512_undef(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <16 x i32> %v, <i32 0, i32 undef, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>
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; CHECK-NEXT: ret <16 x i32> [[TMP1]]
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;
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%1 = insertelement <16 x i32> <i32 0, i32 8, i32 16, i32 24, i32 32, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 24, i32 32, i32 24, i32 8, i32 0>, i32 undef, i32 1
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%2 = tail call <16 x i32> @llvm.x86.avx512.psrav.d.512(<16 x i32> %v, <16 x i32> %1)
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ret <16 x i32> %2
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}
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define <2 x i64> @avx512_psrav_q_128_0(<2 x i64> %v) {
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; CHECK-LABEL: @avx512_psrav_q_128_0(
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; CHECK-NEXT: ret <2 x i64> %v
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;
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%1 = tail call <2 x i64> @llvm.x86.avx512.psrav.q.128(<2 x i64> %v, <2 x i64> zeroinitializer)
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ret <2 x i64> %1
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}
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define <4 x i64> @avx512_psrav_q_256_0(<4 x i64> %v) {
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; CHECK-LABEL: @avx512_psrav_q_256_0(
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; CHECK-NEXT: ret <4 x i64> %v
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;
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%1 = tail call <4 x i64> @llvm.x86.avx512.psrav.q.256(<4 x i64> %v, <4 x i64> zeroinitializer)
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ret <4 x i64> %1
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}
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define <2 x i64> @avx512_psrav_q_128_var(<2 x i64> %v) {
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; CHECK-LABEL: @avx512_psrav_q_128_var(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i64> %v, <i64 0, i64 8>
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%1 = tail call <2 x i64> @llvm.x86.avx512.psrav.q.128(<2 x i64> %v, <2 x i64> <i64 0, i64 8>)
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ret <2 x i64> %1
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}
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define <4 x i64> @avx512_psrav_q_256_var(<4 x i64> %v) {
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; CHECK-LABEL: @avx512_psrav_q_256_var(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i64> %v, <i64 0, i64 8, i64 16, i64 31>
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; CHECK-NEXT: ret <4 x i64> [[TMP1]]
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;
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%1 = tail call <4 x i64> @llvm.x86.avx512.psrav.q.256(<4 x i64> %v, <4 x i64> <i64 0, i64 8, i64 16, i64 31>)
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ret <4 x i64> %1
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}
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define <2 x i64> @avx512_psrav_q_128_allbig(<2 x i64> %v) {
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; CHECK-LABEL: @avx512_psrav_q_128_allbig(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i64> %v, <i64 63, i64 undef>
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; CHECK-NEXT: ret <2 x i64> [[TMP1]]
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;
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%1 = tail call <2 x i64> @llvm.x86.avx512.psrav.q.128(<2 x i64> %v, <2 x i64> <i64 64, i64 undef>)
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ret <2 x i64> %1
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}
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define <4 x i64> @avx512_psrav_q_256_allbig(<4 x i64> %v) {
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; CHECK-LABEL: @avx512_psrav_q_256_allbig(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i64> %v, <i64 63, i64 undef, i64 63, i64 63>
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; CHECK-NEXT: ret <4 x i64> [[TMP1]]
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;
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%1 = tail call <4 x i64> @llvm.x86.avx512.psrav.q.256(<4 x i64> %v, <4 x i64> <i64 64, i64 undef, i64 -128, i64 -60>)
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ret <4 x i64> %1
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}
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define <2 x i64> @avx512_psrav_q_128_undef(<2 x i64> %v) {
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; CHECK-LABEL: @avx512_psrav_q_128_undef(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i64> %v, <i64 undef, i64 8>
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; CHECK-NEXT: ret <2 x i64> [[TMP1]]
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;
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%1 = insertelement <2 x i64> <i64 0, i64 8>, i64 undef, i64 0
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%2 = tail call <2 x i64> @llvm.x86.avx512.psrav.q.128(<2 x i64> %v, <2 x i64> %1)
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ret <2 x i64> %2
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}
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define <4 x i64> @avx512_psrav_q_256_undef(<4 x i64> %v) {
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; CHECK-LABEL: @avx512_psrav_q_256_undef(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i64> %v, <i64 undef, i64 8, i64 16, i64 31>
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; CHECK-NEXT: ret <4 x i64> [[TMP1]]
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;
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%1 = insertelement <4 x i64> <i64 0, i64 8, i64 16, i64 31>, i64 undef, i64 0
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%2 = tail call <4 x i64> @llvm.x86.avx512.psrav.q.256(<4 x i64> %v, <4 x i64> %1)
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ret <4 x i64> %2
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}
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define <8 x i64> @avx512_psrav_q_512_0(<8 x i64> %v) {
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; CHECK-LABEL: @avx512_psrav_q_512_0(
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; CHECK-NEXT: ret <8 x i64> %v
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;
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%1 = tail call <8 x i64> @llvm.x86.avx512.psrav.q.512(<8 x i64> %v, <8 x i64> zeroinitializer)
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ret <8 x i64> %1
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}
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define <8 x i64> @avx512_psrav_q_512_var(<8 x i64> %v) {
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; CHECK-LABEL: @avx512_psrav_q_512_var(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i64> %v, <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
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; CHECK-NEXT: ret <8 x i64> [[TMP1]]
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;
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%1 = tail call <8 x i64> @llvm.x86.avx512.psrav.q.512(<8 x i64> %v, <8 x i64> <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>)
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ret <8 x i64> %1
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}
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define <8 x i64> @avx512_psrav_q_512_allbig(<8 x i64> %v) {
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; CHECK-LABEL: @avx512_psrav_q_512_allbig(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i64> %v, <i64 63, i64 undef, i64 63, i64 63, i64 63, i64 undef, i64 63, i64 63>
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; CHECK-NEXT: ret <8 x i64> [[TMP1]]
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;
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%1 = tail call <8 x i64> @llvm.x86.avx512.psrav.q.512(<8 x i64> %v, <8 x i64> <i64 64, i64 undef, i64 -128, i64 -60, i64 64, i64 undef, i64 -128, i64 -60>)
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ret <8 x i64> %1
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}
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define <8 x i64> @avx512_psrav_q_512_undef(<8 x i64> %v) {
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; CHECK-LABEL: @avx512_psrav_q_512_undef(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i64> %v, <i64 undef, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
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; CHECK-NEXT: ret <8 x i64> [[TMP1]]
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;
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%1 = insertelement <8 x i64> <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>, i64 undef, i64 0
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%2 = tail call <8 x i64> @llvm.x86.avx512.psrav.q.512(<8 x i64> %v, <8 x i64> %1)
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ret <8 x i64> %2
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}
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;
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; LSHR - Constant Per-Element Vector
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;
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@ -1800,6 +1942,94 @@ define <4 x i64> @avx2_psrlv_q_256_undef(<4 x i64> %v) {
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ret <4 x i64> %2
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}
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define <16 x i32> @avx2_psrlv_d_512_0(<16 x i32> %v) {
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; CHECK-LABEL: @avx2_psrlv_d_512_0(
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; CHECK-NEXT: ret <16 x i32> %v
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;
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%1 = tail call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> %v, <16 x i32> zeroinitializer)
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ret <16 x i32> %1
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}
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define <16 x i32> @avx512_psrlv_d_512_var(<16 x i32> %v) {
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; CHECK-LABEL: @avx512_psrlv_d_512_var(
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; CHECK-NEXT: [[TMP1:%.*]] = lshr <16 x i32> %v, <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>
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; CHECK-NEXT: ret <16 x i32> [[TMP1]]
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;
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%1 = tail call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> %v, <16 x i32> <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>)
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ret <16 x i32> %1
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}
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define <16 x i32> @avx512_psrlv_d_512_big(<16 x i32> %v) {
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; CHECK-LABEL: @avx512_psrlv_d_512_big(
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; CHECK-NEXT: [[TMP1:%.*]] = tail call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> %v, <16 x i32> <i32 0, i32 8, i32 16, i32 64, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 64, i32 31, i32 24, i32 8, i32 0>)
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; CHECK-NEXT: ret <16 x i32> [[TMP1]]
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;
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%1 = tail call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> %v, <16 x i32> <i32 0, i32 8, i32 16, i32 64, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 64, i32 31, i32 24, i32 8, i32 0>)
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ret <16 x i32> %1
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}
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define <16 x i32> @avx512_psrlv_d_512_allbig(<16 x i32> %v) {
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; CHECK-LABEL: @avx512_psrlv_d_512_allbig(
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; CHECK-NEXT: ret <16 x i32> <i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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;
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%1 = tail call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> %v, <16 x i32> <i32 undef, i32 100, i32 255, i32 55555, i32 -32, i32 -100, i32 -255, i32 -55555, i32 undef, i32 100, i32 255, i32 55555, i32 -32, i32 -100, i32 -255, i32 -55555>)
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ret <16 x i32> %1
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}
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define <16 x i32> @avx512_psrlv_d_512_undef(<16 x i32> %v) {
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; CHECK-LABEL: @avx512_psrlv_d_512_undef(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = lshr <16 x i32> %v, <i32 0, i32 undef, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
|
||||
; CHECK-NEXT: ret <16 x i32> [[TMP1]]
|
||||
;
|
||||
%1 = insertelement <16 x i32> <i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>, i32 undef, i32 1
|
||||
%2 = tail call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> %v, <16 x i32> %1)
|
||||
ret <16 x i32> %2
|
||||
}
|
||||
|
||||
define <8 x i64> @avx512_psrlv_q_512_0(<8 x i64> %v) {
|
||||
; CHECK-LABEL: @avx512_psrlv_q_512_0(
|
||||
; CHECK-NEXT: ret <8 x i64> %v
|
||||
;
|
||||
%1 = tail call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> %v, <8 x i64> zeroinitializer)
|
||||
ret <8 x i64> %1
|
||||
}
|
||||
|
||||
define <8 x i64> @avx512_psrlv_q_512_var(<8 x i64> %v) {
|
||||
; CHECK-LABEL: @avx512_psrlv_q_512_var(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i64> %v, <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
|
||||
; CHECK-NEXT: ret <8 x i64> [[TMP1]]
|
||||
;
|
||||
%1 = tail call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> %v, <8 x i64> <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>)
|
||||
ret <8 x i64> %1
|
||||
}
|
||||
|
||||
define <8 x i64> @avx512_psrlv_q_512_big(<8 x i64> %v) {
|
||||
; CHECK-LABEL: @avx512_psrlv_q_512_big(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> %v, <8 x i64> <i64 0, i64 8, i64 16, i64 64, i64 0, i64 8, i64 16, i64 64>)
|
||||
; CHECK-NEXT: ret <8 x i64> [[TMP1]]
|
||||
;
|
||||
%1 = tail call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> %v, <8 x i64> <i64 0, i64 8, i64 16, i64 64, i64 0, i64 8, i64 16, i64 64>)
|
||||
ret <8 x i64> %1
|
||||
}
|
||||
|
||||
define <8 x i64> @avx512_psrlv_q_512_allbig(<8 x i64> %v) {
|
||||
; CHECK-LABEL: @avx512_psrlv_q_512_allbig(
|
||||
; CHECK-NEXT: ret <8 x i64> <i64 0, i64 undef, i64 0, i64 0, i64 0, i64 undef, i64 0, i64 0>
|
||||
;
|
||||
%1 = tail call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> %v, <8 x i64> <i64 64, i64 undef, i64 -128, i64 -60, i64 64, i64 undef, i64 -128, i64 -60>)
|
||||
ret <8 x i64> %1
|
||||
}
|
||||
|
||||
define <8 x i64> @avx512_psrlv_q_512_undef(<8 x i64> %v) {
|
||||
; CHECK-LABEL: @avx512_psrlv_q_512_undef(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i64> %v, <i64 undef, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
|
||||
; CHECK-NEXT: ret <8 x i64> [[TMP1]]
|
||||
;
|
||||
%1 = insertelement <8 x i64> <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>, i64 undef, i64 0
|
||||
%2 = tail call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> %v, <8 x i64> %1)
|
||||
ret <8 x i64> %2
|
||||
}
|
||||
|
||||
;
|
||||
; SHL - Constant Per-Element Vector
|
||||
;
|
||||
|
|
@ -1980,6 +2210,94 @@ define <4 x i64> @avx2_psllv_q_256_undef(<4 x i64> %v) {
|
|||
ret <4 x i64> %2
|
||||
}
|
||||
|
||||
define <16 x i32> @avx512_psllv_d_512_0(<16 x i32> %v) {
|
||||
; CHECK-LABEL: @avx512_psllv_d_512_0(
|
||||
; CHECK-NEXT: ret <16 x i32> %v
|
||||
;
|
||||
%1 = tail call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> %v, <16 x i32> zeroinitializer)
|
||||
ret <16 x i32> %1
|
||||
}
|
||||
|
||||
define <16 x i32> @avx512_psllv_d_512_var(<16 x i32> %v) {
|
||||
; CHECK-LABEL: @avx512_psllv_d_512_var(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shl <16 x i32> %v, <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>
|
||||
; CHECK-NEXT: ret <16 x i32> [[TMP1]]
|
||||
;
|
||||
%1 = tail call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> %v, <16 x i32> <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>)
|
||||
ret <16 x i32> %1
|
||||
}
|
||||
|
||||
define <16 x i32> @avx512_psllv_d_512_big(<16 x i32> %v) {
|
||||
; CHECK-LABEL: @avx512_psllv_d_512_big(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> %v, <16 x i32> <i32 0, i32 8, i32 16, i32 64, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 64, i32 31, i32 24, i32 8, i32 0>)
|
||||
; CHECK-NEXT: ret <16 x i32> [[TMP1]]
|
||||
;
|
||||
%1 = tail call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> %v, <16 x i32> <i32 0, i32 8, i32 16, i32 64, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 64, i32 31, i32 24, i32 8, i32 0>)
|
||||
ret <16 x i32> %1
|
||||
}
|
||||
|
||||
define <16 x i32> @avx512_psllv_d_512_allbig(<16 x i32> %v) {
|
||||
; CHECK-LABEL: @avx512_psllv_d_512_allbig(
|
||||
; CHECK-NEXT: ret <16 x i32> <i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
|
||||
;
|
||||
%1 = tail call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> %v, <16 x i32> <i32 undef, i32 100, i32 255, i32 55555, i32 -32, i32 -100, i32 -255, i32 -55555, i32 undef, i32 100, i32 255, i32 55555, i32 -32, i32 -100, i32 -255, i32 -55555>)
|
||||
ret <16 x i32> %1
|
||||
}
|
||||
|
||||
define <16 x i32> @avx512_psllv_d_512_undef(<16 x i32> %v) {
|
||||
; CHECK-LABEL: @avx512_psllv_d_512_undef(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shl <16 x i32> %v, <i32 0, i32 undef, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
|
||||
; CHECK-NEXT: ret <16 x i32> [[TMP1]]
|
||||
;
|
||||
%1 = insertelement <16 x i32> <i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>, i32 undef, i32 1
|
||||
%2 = tail call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> %v, <16 x i32> %1)
|
||||
ret <16 x i32> %2
|
||||
}
|
||||
|
||||
define <8 x i64> @avx512_psllv_q_512_0(<8 x i64> %v) {
|
||||
; CHECK-LABEL: @avx512_psllv_q_512_0(
|
||||
; CHECK-NEXT: ret <8 x i64> %v
|
||||
;
|
||||
%1 = tail call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> %v, <8 x i64> zeroinitializer)
|
||||
ret <8 x i64> %1
|
||||
}
|
||||
|
||||
define <8 x i64> @avx512_psllv_q_512_var(<8 x i64> %v) {
|
||||
; CHECK-LABEL: @avx512_psllv_q_512_var(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i64> %v, <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
|
||||
; CHECK-NEXT: ret <8 x i64> [[TMP1]]
|
||||
;
|
||||
%1 = tail call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> %v, <8 x i64> <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>)
|
||||
ret <8 x i64> %1
|
||||
}
|
||||
|
||||
define <8 x i64> @avx512_psllv_q_512_big(<8 x i64> %v) {
|
||||
; CHECK-LABEL: @avx512_psllv_q_512_big(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> %v, <8 x i64> <i64 0, i64 8, i64 16, i64 64, i64 0, i64 8, i64 16, i64 64>)
|
||||
; CHECK-NEXT: ret <8 x i64> [[TMP1]]
|
||||
;
|
||||
%1 = tail call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> %v, <8 x i64> <i64 0, i64 8, i64 16, i64 64, i64 0, i64 8, i64 16, i64 64>)
|
||||
ret <8 x i64> %1
|
||||
}
|
||||
|
||||
define <8 x i64> @avx512_psllv_q_512_allbig(<8 x i64> %v) {
|
||||
; CHECK-LABEL: @avx512_psllv_q_512_allbig(
|
||||
; CHECK-NEXT: ret <8 x i64> <i64 0, i64 undef, i64 0, i64 0, i64 0, i64 undef, i64 0, i64 0>
|
||||
;
|
||||
%1 = tail call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> %v, <8 x i64> <i64 64, i64 undef, i64 -128, i64 -60, i64 64, i64 undef, i64 -128, i64 -60>)
|
||||
ret <8 x i64> %1
|
||||
}
|
||||
|
||||
define <8 x i64> @avx512_psllv_q_512_undef(<8 x i64> %v) {
|
||||
; CHECK-LABEL: @avx512_psllv_q_512_undef(
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i64> %v, <i64 undef, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
|
||||
; CHECK-NEXT: ret <8 x i64> [[TMP1]]
|
||||
;
|
||||
%1 = insertelement <8 x i64> <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>, i64 undef, i64 0
|
||||
%2 = tail call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> %v, <8 x i64> %1)
|
||||
ret <8 x i64> %2
|
||||
}
|
||||
|
||||
;
|
||||
; Vector Demanded Bits
|
||||
;
|
||||
|
|
@ -2710,15 +3028,23 @@ declare <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16>, <8 x i16>) #1
|
|||
|
||||
declare <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32>, <4 x i32>) #1
|
||||
declare <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32>, <8 x i32>) #1
|
||||
declare <16 x i32> @llvm.x86.avx512.psrav.d.512(<16 x i32>, <16 x i32>) #1
|
||||
declare <2 x i64> @llvm.x86.avx512.psrav.q.128(<2 x i64>, <2 x i64>) #1
|
||||
declare <4 x i64> @llvm.x86.avx512.psrav.q.256(<4 x i64>, <4 x i64>) #1
|
||||
declare <8 x i64> @llvm.x86.avx512.psrav.q.512(<8 x i64>, <8 x i64>) #1
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32>, <4 x i32>) #1
|
||||
declare <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32>, <8 x i32>) #1
|
||||
declare <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64>, <2 x i64>) #1
|
||||
declare <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64>, <4 x i64>) #1
|
||||
declare <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32>, <16 x i32>) #1
|
||||
declare <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64>, <8 x i64>) #1
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32>, <4 x i32>) #1
|
||||
declare <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32>, <8 x i32>) #1
|
||||
declare <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64>, <2 x i64>) #1
|
||||
declare <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64>, <4 x i64>) #1
|
||||
declare <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32>, <16 x i32>) #1
|
||||
declare <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64>, <8 x i64>) #1
|
||||
|
||||
attributes #1 = { nounwind readnone }
|
||||
|
|
|
|||
Loading…
Reference in New Issue