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Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. 

crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and
crc64.[8|16|32] have been renamed to .crc32.64.[8|64].

llvm-svn: 132163
This commit is contained in:
Chad Rosier 2011-05-26 23:13:19 +00:00
parent 017b959ad5
commit b362884ca9
8 changed files with 96 additions and 48 deletions
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10
llvm/include/llvm/IntrinsicsX86.td
View File

@ -948,19 +948,19 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
// Miscellaneous
// CRC Instruction
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse42_crc32_8 : GCCBuiltin<"__builtin_ia32_crc32qi">,
def int_x86_sse42_crc32_32_8 : GCCBuiltin<"__builtin_ia32_crc32qi">,
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i8_ty],
[IntrNoMem]>;
def int_x86_sse42_crc32_16 : GCCBuiltin<"__builtin_ia32_crc32hi">,
def int_x86_sse42_crc32_32_16 : GCCBuiltin<"__builtin_ia32_crc32hi">,
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i16_ty],
[IntrNoMem]>;
def int_x86_sse42_crc32_32 : GCCBuiltin<"__builtin_ia32_crc32si">,
def int_x86_sse42_crc32_32_32 : GCCBuiltin<"__builtin_ia32_crc32si">,
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
[IntrNoMem]>;
def int_x86_sse42_crc64_8 :
def int_x86_sse42_crc32_64_8 :
Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i8_ty],
[IntrNoMem]>;
def int_x86_sse42_crc64_64 : GCCBuiltin<"__builtin_ia32_crc32di">,
def int_x86_sse42_crc32_64_64 : GCCBuiltin<"__builtin_ia32_crc32di">,
Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
[IntrNoMem]>;
}

4
llvm/lib/Analysis/ValueTracking.cpp
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@ -680,8 +680,8 @@ void llvm::ComputeMaskedBits(Value *V, const APInt &Mask,
KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits);
break;
}
case Intrinsic::x86_sse42_crc64_8:
case Intrinsic::x86_sse42_crc64_64:
case Intrinsic::x86_sse42_crc32_64_8:
case Intrinsic::x86_sse42_crc32_64_64:
KnownZero = APInt::getHighBitsSet(64, 32);
break;
}

40
llvm/lib/Target/X86/X86InstrSSE.td
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@ -4935,66 +4935,66 @@ defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
// This set of instructions are only rm, the only difference is the size
// of r and m.
let Constraints = "$src1 = $dst" in {
def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
(ins GR32:$src1, i8mem:$src2),
"crc32{b} \t{$src2, $src1|$src1, $src2}",
[(set GR32:$dst,
(int_x86_sse42_crc32_8 GR32:$src1,
(int_x86_sse42_crc32_32_8 GR32:$src1,
(load addr:$src2)))]>;
def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
(ins GR32:$src1, GR8:$src2),
"crc32{b} \t{$src2, $src1|$src1, $src2}",
[(set GR32:$dst,
(int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;
def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
(int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
(ins GR32:$src1, i16mem:$src2),
"crc32{w} \t{$src2, $src1|$src1, $src2}",
[(set GR32:$dst,
(int_x86_sse42_crc32_16 GR32:$src1,
(int_x86_sse42_crc32_32_16 GR32:$src1,
(load addr:$src2)))]>,
OpSize;
def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
(ins GR32:$src1, GR16:$src2),
"crc32{w} \t{$src2, $src1|$src1, $src2}",
[(set GR32:$dst,
(int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
(int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
OpSize;
def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
(ins GR32:$src1, i32mem:$src2),
"crc32{l} \t{$src2, $src1|$src1, $src2}",
[(set GR32:$dst,
(int_x86_sse42_crc32_32 GR32:$src1,
(int_x86_sse42_crc32_32_32 GR32:$src1,
(load addr:$src2)))]>;
def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
(ins GR32:$src1, GR32:$src2),
"crc32{l} \t{$src2, $src1|$src1, $src2}",
[(set GR32:$dst,
(int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;
def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
(int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
(ins GR64:$src1, i8mem:$src2),
"crc32{b} \t{$src2, $src1|$src1, $src2}",
[(set GR64:$dst,
(int_x86_sse42_crc64_8 GR64:$src1,
(int_x86_sse42_crc32_64_8 GR64:$src1,
(load addr:$src2)))]>,
REX_W;
def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
(ins GR64:$src1, GR8:$src2),
"crc32{b} \t{$src2, $src1|$src1, $src2}",
[(set GR64:$dst,
(int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,
(int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
REX_W;
def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
(ins GR64:$src1, i64mem:$src2),
"crc32{q} \t{$src2, $src1|$src1, $src2}",
[(set GR64:$dst,
(int_x86_sse42_crc64_64 GR64:$src1,
(int_x86_sse42_crc32_64_64 GR64:$src1,
(load addr:$src2)))]>,
REX_W;
def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
(ins GR64:$src1, GR64:$src2),
"crc32{q} \t{$src2, $src1|$src1, $src2}",
[(set GR64:$dst,
(int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,
(int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
REX_W;
}

4
llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
View File

@ -780,8 +780,8 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
// TODO: Could compute known zero/one bits based on the input.
break;
}
case Intrinsic::x86_sse42_crc64_8:
case Intrinsic::x86_sse42_crc64_64:
case Intrinsic::x86_sse42_crc32_64_8:
case Intrinsic::x86_sse42_crc32_64_64:
KnownZero = APInt::getHighBitsSet(64, 32);
return 0;
}

28
llvm/lib/VMCore/AutoUpgrade.cpp
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@ -285,7 +285,33 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) {
}
break;
case 'x':
case 'x':
// This fixes the poorly named crc32 intrinsics
if (Name.compare(5, 13, "x86.sse42.crc", 13) == 0) {
const char* NewFnName = NULL;
if (Name.compare(18, 2, "32", 2) == 0) {
if (Name.compare(20, 2, ".8") == 0) {
NewFnName = "llvm.x86.sse42.crc32.32.8";
} else if (Name.compare(20, 2, ".16") == 0) {
NewFnName = "llvm.x86.sse42.crc32.32.16";
} else if (Name.compare(20, 2, ".32") == 0) {
NewFnName = "llvm.x86.sse42.crc32.32.32";
}
}
else if (Name.compare(18, 2, "64", 2) == 0) {
if (Name.compare(20, 2, ".8") == 0) {
NewFnName = "llvm.x86.sse42.crc32.64.8";
} else if (Name.compare(20, 2, ".64") == 0) {
NewFnName = "llvm.x86.sse42.crc32.64.64";
}
}
if (NewFnName) {
F->setName(NewFnName);
NewFn = F;
return true;
}
}
// This fixes all MMX shift intrinsic instructions to take a
// x86_mmx instead of a v1i64, v2i32, v4i16, or v8i8.
if (Name.compare(5, 8, "x86.mmx.", 8) == 0) {

31
llvm/test/CodeGen/X86/sse42.ll
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@ -1,38 +1,39 @@
; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X64
declare i32 @llvm.x86.sse42.crc32.8(i32, i8) nounwind
declare i32 @llvm.x86.sse42.crc32.16(i32, i16) nounwind
declare i32 @llvm.x86.sse42.crc32.32(i32, i32) nounwind
declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8) nounwind
declare i32 @llvm.x86.sse42.crc32.32.16(i32, i16) nounwind
declare i32 @llvm.x86.sse42.crc32.32.32(i32, i32) nounwind
define i32 @crc32_8(i32 %a, i8 %b) nounwind {
%tmp = call i32 @llvm.x86.sse42.crc32.8(i32 %a, i8 %b)
define i32 @crc32_32_8(i32 %a, i8 %b) nounwind {
%tmp = call i32 @llvm.x86.sse42.crc32.32.8(i32 %a, i8 %b)
ret i32 %tmp
; X32: _crc32_8:
; X32: _crc32_32_8:
; X32: crc32b 8(%esp), %eax
; X64: _crc32_8:
; X64: _crc32_32_8:
; X64: crc32b %sil,
}
define i32 @crc32_16(i32 %a, i16 %b) nounwind {
%tmp = call i32 @llvm.x86.sse42.crc32.16(i32 %a, i16 %b)
define i32 @crc32_32_16(i32 %a, i16 %b) nounwind {
%tmp = call i32 @llvm.x86.sse42.crc32.32.16(i32 %a, i16 %b)
ret i32 %tmp
; X32: _crc32_16:
; X32: _crc32_32_16:
; X32: crc32w 8(%esp), %eax
; X64: _crc32_16:
; X64: _crc32_32_16:
; X64: crc32w %si,
}
define i32 @crc32_32(i32 %a, i32 %b) nounwind {
%tmp = call i32 @llvm.x86.sse42.crc32.32(i32 %a, i32 %b)
define i32 @crc32_32_32(i32 %a, i32 %b) nounwind {
%tmp = call i32 @llvm.x86.sse42.crc32.32.32(i32 %a, i32 %b)
ret i32 %tmp
; X32: _crc32_32:
; X32: _crc32_32_32:
; X32: crc32l 8(%esp), %eax
; X64: _crc32_32:
; X64: _crc32_32_32:
; X64: crc32l %esi,
}

21
llvm/test/CodeGen/X86/sse42_64.ll Normal file
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@ -0,0 +1,21 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X64
declare i64 @llvm.x86.sse42.crc32.64.8(i64, i8) nounwind
declare i64 @llvm.x86.sse42.crc32.64.64(i64, i64) nounwind
define i64 @crc32_64_8(i64 %a, i8 %b) nounwind {
%tmp = call i64 @llvm.x86.sse42.crc32.64.8(i64 %a, i8 %b)
ret i64 %tmp
; X64: _crc32_64_8:
; X64: crc32b %sil,
}
define i64 @crc32_64_64(i64 %a, i64 %b) nounwind {
%tmp = call i64 @llvm.x86.sse42.crc32.64.64(i64 %a, i64 %b)
ret i64 %tmp
; X64: _crc32_64_64:
; X64: crc32q %rsi,
}

6
llvm/test/Transforms/InstCombine/x86-crc32-demanded.ll
View File

@ -6,12 +6,12 @@
define i64 @test() nounwind {
entry:
; CHECK: test
; CHECK: tail call i64 @llvm.x86.sse42.crc64.64
; CHECK: tail call i64 @llvm.x86.sse42.crc32.64.64
; CHECK-NOT: and
; CHECK: ret
%0 = tail call i64 @llvm.x86.sse42.crc64.64(i64 0, i64 4) nounwind
%0 = tail call i64 @llvm.x86.sse42.crc32.64.64(i64 0, i64 4) nounwind
%1 = and i64 %0, 4294967295
ret i64 %1
}
declare i64 @llvm.x86.sse42.crc64.64(i64, i64) nounwind readnone
declare i64 @llvm.x86.sse42.crc32.64.64(i64, i64) nounwind readnone