[mips] Add new InstrItinClasses for move from/to coprocessor instructions and
floating point loads and stores. No changes in functionality. llvm-svn: 185399
This commit is contained in:
Akira Hatanaka
parent
8466ca86fe
commit
b34ad7860f
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@ -131,17 +131,17 @@ let Predicates = [HasMips64r2, HasStdEnc],
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let DecoderNamespace = "Mips64" in {
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/// Load and Store Instructions
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/// aligned
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defm LB64 : LoadM<"lb", CPU64Regs, sextloadi8>, LW_FM<0x20>;
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defm LBu64 : LoadM<"lbu", CPU64Regs, zextloadi8>, LW_FM<0x24>;
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defm LH64 : LoadM<"lh", CPU64Regs, sextloadi16>, LW_FM<0x21>;
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defm LHu64 : LoadM<"lhu", CPU64Regs, zextloadi16>, LW_FM<0x25>;
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defm LW64 : LoadM<"lw", CPU64Regs, sextloadi32>, LW_FM<0x23>;
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defm LWu64 : LoadM<"lwu", CPU64Regs, zextloadi32>, LW_FM<0x27>;
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defm SB64 : StoreM<"sb", CPU64Regs, truncstorei8>, LW_FM<0x28>;
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defm SH64 : StoreM<"sh", CPU64Regs, truncstorei16>, LW_FM<0x29>;
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defm SW64 : StoreM<"sw", CPU64Regs, truncstorei32>, LW_FM<0x2b>;
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defm LD : LoadM<"ld", CPU64Regs, load>, LW_FM<0x37>;
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defm SD : StoreM<"sd", CPU64Regs, store>, LW_FM<0x3f>;
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defm LB64 : LoadM<"lb", CPU64Regs, sextloadi8, IILoad>, LW_FM<0x20>;
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defm LBu64 : LoadM<"lbu", CPU64Regs, zextloadi8, IILoad>, LW_FM<0x24>;
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defm LH64 : LoadM<"lh", CPU64Regs, sextloadi16, IILoad>, LW_FM<0x21>;
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defm LHu64 : LoadM<"lhu", CPU64Regs, zextloadi16, IILoad>, LW_FM<0x25>;
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defm LW64 : LoadM<"lw", CPU64Regs, sextloadi32, IILoad>, LW_FM<0x23>;
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defm LWu64 : LoadM<"lwu", CPU64Regs, zextloadi32, IILoad>, LW_FM<0x27>;
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defm SB64 : StoreM<"sb", CPU64Regs, truncstorei8, IIStore>, LW_FM<0x28>;
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defm SH64 : StoreM<"sh", CPU64Regs, truncstorei16, IIStore>, LW_FM<0x29>;
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defm SW64 : StoreM<"sw", CPU64Regs, truncstorei32, IIStore>, LW_FM<0x2b>;
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defm LD : LoadM<"ld", CPU64Regs, load, IILoad>, LW_FM<0x37>;
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defm SD : StoreM<"sd", CPU64Regs, store, IIStore>, LW_FM<0x3f>;
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/// load/store left/right
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defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64Regs>, LW_FM<0x22>;
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@ -289,10 +289,12 @@ defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>;
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/// Move Control Registers From/To CPU Registers
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def CFC1 : MFC1_FT_CCR<"cfc1", CPURegs, CCROpnd, IIFmove>, MFC1_FM<2>;
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def CTC1 : MTC1_FT_CCR<"ctc1", CCROpnd, CPURegs, IIFmove>, MFC1_FM<6>;
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def MFC1 : MFC1_FT<"mfc1", CPURegs, FGR32, IIFmove, bitconvert>, MFC1_FM<0>;
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def MTC1 : MTC1_FT<"mtc1", FGR32, CPURegs, IIFmove, bitconvert>, MFC1_FM<4>;
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def DMFC1 : MFC1_FT<"dmfc1", CPU64Regs, FGR64, IIFmove, bitconvert>, MFC1_FM<1>;
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def DMTC1 : MTC1_FT<"dmtc1", FGR64, CPU64Regs, IIFmove, bitconvert>, MFC1_FM<5>;
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def MFC1 : MFC1_FT<"mfc1", CPURegs, FGR32, IIFmoveC1, bitconvert>, MFC1_FM<0>;
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def MTC1 : MTC1_FT<"mtc1", FGR32, CPURegs, IIFmoveC1, bitconvert>, MFC1_FM<4>;
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def DMFC1 : MFC1_FT<"dmfc1", CPU64Regs, FGR64, IIFmoveC1, bitconvert>,
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MFC1_FM<1>;
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def DMTC1 : MTC1_FT<"dmtc1", FGR64, CPU64Regs, IIFmoveC1, bitconvert>,
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MFC1_FM<5>;
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def FMOV_S : ABSS_FT<"mov.s", FGR32, FGR32, IIFmove>, ABSS_FM<0x6, 16>;
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def FMOV_D32 : ABSS_FT<"mov.d", AFGR64, AFGR64, IIFmove>, ABSS_FM<0x6, 17>,
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@ -304,86 +306,86 @@ def FMOV_D64 : ABSS_FT<"mov.d", FGR64, FGR64, IIFmove>, ABSS_FM<0x6, 17>,
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/// Floating Point Memory Instructions
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let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
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def LWC1_P8 : LW_FT<"lwc1", FGR32RegsOpnd, IILoad, mem64, load>, LW_FM<0x31>;
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def SWC1_P8 : SW_FT<"swc1", FGR32RegsOpnd, IIStore, mem64, store>,
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def LWC1_P8 : LW_FT<"lwc1", FGR32RegsOpnd, IIFLoad, mem64, load>, LW_FM<0x31>;
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def SWC1_P8 : SW_FT<"swc1", FGR32RegsOpnd, IIFStore, mem64, store>,
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LW_FM<0x39>;
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def LDC164_P8 : LW_FT<"ldc1", FGR64RegsOpnd, IILoad, mem64, load>,
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def LDC164_P8 : LW_FT<"ldc1", FGR64RegsOpnd, IIFLoad, mem64, load>,
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LW_FM<0x35> {
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let isCodeGenOnly =1;
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}
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def SDC164_P8 : SW_FT<"sdc1", FGR64RegsOpnd, IIStore, mem64, store>,
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def SDC164_P8 : SW_FT<"sdc1", FGR64RegsOpnd, IIFStore, mem64, store>,
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LW_FM<0x3d> {
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let isCodeGenOnly =1;
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}
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}
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let Predicates = [NotN64, HasStdEnc] in {
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def LWC1 : LW_FT<"lwc1", FGR32RegsOpnd, IILoad, mem, load>, LW_FM<0x31>;
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def SWC1 : SW_FT<"swc1", FGR32RegsOpnd, IIStore, mem, store>, LW_FM<0x39>;
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def LWC1 : LW_FT<"lwc1", FGR32RegsOpnd, IIFLoad, mem, load>, LW_FM<0x31>;
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def SWC1 : SW_FT<"swc1", FGR32RegsOpnd, IIFStore, mem, store>, LW_FM<0x39>;
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}
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let Predicates = [NotN64, HasMips64, HasStdEnc],
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DecoderNamespace = "Mips64" in {
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def LDC164 : LW_FT<"ldc1", FGR64RegsOpnd, IILoad, mem, load>, LW_FM<0x35>;
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def SDC164 : SW_FT<"sdc1", FGR64RegsOpnd, IIStore, mem, store>, LW_FM<0x3d>;
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def LDC164 : LW_FT<"ldc1", FGR64RegsOpnd, IIFLoad, mem, load>, LW_FM<0x35>;
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def SDC164 : SW_FT<"sdc1", FGR64RegsOpnd, IIFStore, mem, store>, LW_FM<0x3d>;
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}
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let Predicates = [NotN64, NotMips64, HasStdEnc] in {
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let isPseudo = 1, isCodeGenOnly = 1 in {
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def PseudoLDC1 : LW_FT<"", AFGR64RegsOpnd, IILoad, mem, load>;
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def PseudoSDC1 : SW_FT<"", AFGR64RegsOpnd, IIStore, mem, store>;
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def PseudoLDC1 : LW_FT<"", AFGR64RegsOpnd, IIFLoad, mem, load>;
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def PseudoSDC1 : SW_FT<"", AFGR64RegsOpnd, IIFStore, mem, store>;
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}
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def LDC1 : LW_FT<"ldc1", AFGR64RegsOpnd, IILoad, mem>, LW_FM<0x35>;
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def SDC1 : SW_FT<"sdc1", AFGR64RegsOpnd, IIStore, mem>, LW_FM<0x3d>;
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def LDC1 : LW_FT<"ldc1", AFGR64RegsOpnd, IIFLoad, mem>, LW_FM<0x35>;
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def SDC1 : SW_FT<"sdc1", AFGR64RegsOpnd, IIFStore, mem>, LW_FM<0x3d>;
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}
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// Indexed loads and stores.
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let Predicates = [HasFPIdx, HasStdEnc] in {
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def LWXC1 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, CPURegsOpnd, IILoad, load>,
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def LWXC1 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, CPURegsOpnd, IIFLoad, load>,
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LWXC1_FM<0>;
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def SWXC1 : SWXC1_FT<"swxc1", FGR32RegsOpnd, CPURegsOpnd, IIStore, store>,
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def SWXC1 : SWXC1_FT<"swxc1", FGR32RegsOpnd, CPURegsOpnd, IIFStore, store>,
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SWXC1_FM<8>;
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}
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let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in {
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def LDXC1 : LWXC1_FT<"ldxc1", AFGR64RegsOpnd, CPURegsOpnd, IILoad, load>,
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def LDXC1 : LWXC1_FT<"ldxc1", AFGR64RegsOpnd, CPURegsOpnd, IIFLoad, load>,
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LWXC1_FM<1>;
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def SDXC1 : SWXC1_FT<"sdxc1", AFGR64RegsOpnd, CPURegsOpnd, IIStore, store>,
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def SDXC1 : SWXC1_FT<"sdxc1", AFGR64RegsOpnd, CPURegsOpnd, IIFStore, store>,
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SWXC1_FM<9>;
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}
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let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in {
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def LDXC164 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, CPURegsOpnd, IILoad, load>,
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def LDXC164 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, CPURegsOpnd, IIFLoad, load>,
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LWXC1_FM<1>;
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def SDXC164 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, CPURegsOpnd, IIStore, store>,
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def SDXC164 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, CPURegsOpnd, IIFStore, store>,
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SWXC1_FM<9>;
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}
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// n64
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let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in {
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def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, CPU64RegsOpnd, IILoad, load>,
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def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32RegsOpnd, CPU64RegsOpnd, IIFLoad, load>,
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LWXC1_FM<0>;
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def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, CPU64RegsOpnd, IILoad,
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def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64RegsOpnd, CPU64RegsOpnd, IIFLoad,
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load>, LWXC1_FM<1>;
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def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32RegsOpnd, CPU64RegsOpnd, IIStore,
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def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32RegsOpnd, CPU64RegsOpnd, IIFStore,
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store>, SWXC1_FM<8>;
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def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, CPU64RegsOpnd, IIStore,
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def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64RegsOpnd, CPU64RegsOpnd, IIFStore,
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store>, SWXC1_FM<9>;
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}
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// Load/store doubleword indexed unaligned.
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let Predicates = [NotMips64, HasStdEnc] in {
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def LUXC1 : LWXC1_FT<"luxc1", AFGR64RegsOpnd, CPURegsOpnd, IILoad>,
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def LUXC1 : LWXC1_FT<"luxc1", AFGR64RegsOpnd, CPURegsOpnd, IIFLoad>,
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LWXC1_FM<0x5>;
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def SUXC1 : SWXC1_FT<"suxc1", AFGR64RegsOpnd, CPURegsOpnd, IIStore>,
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def SUXC1 : SWXC1_FT<"suxc1", AFGR64RegsOpnd, CPURegsOpnd, IIFStore>,
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SWXC1_FM<0xd>;
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}
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let Predicates = [HasMips64, HasStdEnc],
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DecoderNamespace="Mips64" in {
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def LUXC164 : LWXC1_FT<"luxc1", FGR64RegsOpnd, CPURegsOpnd, IILoad>,
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def LUXC164 : LWXC1_FT<"luxc1", FGR64RegsOpnd, CPURegsOpnd, IIFLoad>,
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LWXC1_FM<0x5>;
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def SUXC164 : SWXC1_FT<"suxc1", FGR64RegsOpnd, CPURegsOpnd, IIStore>,
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def SUXC164 : SWXC1_FT<"suxc1", FGR64RegsOpnd, CPURegsOpnd, IIFStore>,
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SWXC1_FM<0xd>;
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}
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@ -443,7 +443,8 @@ class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
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// Memory Load/Store
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class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC,
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Operand MemOpnd, ComplexPattern Addr, string ofsuffix> :
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InstrItinClass Itin, Operand MemOpnd, ComplexPattern Addr,
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string ofsuffix> :
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InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
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[(set RC:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI,
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!strconcat(opstr, ofsuffix)> {
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@ -453,7 +454,8 @@ class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC,
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}
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class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC,
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Operand MemOpnd, ComplexPattern Addr, string ofsuffix> :
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InstrItinClass Itin, Operand MemOpnd, ComplexPattern Addr,
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string ofsuffix> :
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InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
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[(OpNode RC:$rt, Addr:$addr)], NoItinerary, FrmI,
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!strconcat(opstr, ofsuffix)> {
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@ -463,10 +465,11 @@ class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC,
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multiclass LoadM<string opstr, RegisterClass RC,
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SDPatternOperator OpNode = null_frag,
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InstrItinClass Itin = NoItinerary,
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ComplexPattern Addr = addr> {
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def NAME : Load<opstr, OpNode, RC, mem, Addr, "">,
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def NAME : Load<opstr, OpNode, RC, Itin, mem, Addr, "">,
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Requires<[NotN64, HasStdEnc]>;
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def _P8 : Load<opstr, OpNode, RC, mem64, Addr, "_p8">,
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def _P8 : Load<opstr, OpNode, RC, Itin, mem64, Addr, "_p8">,
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Requires<[IsN64, HasStdEnc]> {
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let DecoderNamespace = "Mips64";
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let isCodeGenOnly = 1;
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@ -475,10 +478,11 @@ multiclass LoadM<string opstr, RegisterClass RC,
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multiclass StoreM<string opstr, RegisterClass RC,
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SDPatternOperator OpNode = null_frag,
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InstrItinClass Itin = NoItinerary,
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ComplexPattern Addr = addr> {
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def NAME : Store<opstr, OpNode, RC, mem, Addr, "">,
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def NAME : Store<opstr, OpNode, RC, Itin, mem, Addr, "">,
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Requires<[NotN64, HasStdEnc]>;
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def _P8 : Store<opstr, OpNode, RC, mem64, Addr, "_p8">,
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def _P8 : Store<opstr, OpNode, RC, Itin, mem64, Addr, "_p8">,
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Requires<[IsN64, HasStdEnc]> {
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let DecoderNamespace = "Mips64";
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let isCodeGenOnly = 1;
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@ -917,14 +921,16 @@ let Predicates = [HasMips32r2, HasStdEnc] in {
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/// Load and Store Instructions
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/// aligned
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defm LB : LoadM<"lb", CPURegs, sextloadi8>, MMRel, LW_FM<0x20>;
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defm LBu : LoadM<"lbu", CPURegs, zextloadi8, addrDefault>, MMRel, LW_FM<0x24>;
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defm LH : LoadM<"lh", CPURegs, sextloadi16, addrDefault>, MMRel, LW_FM<0x21>;
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defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, MMRel, LW_FM<0x25>;
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defm LW : LoadM<"lw", CPURegs, load, addrDefault>, MMRel, LW_FM<0x23>;
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defm SB : StoreM<"sb", CPURegs, truncstorei8>, MMRel, LW_FM<0x28>;
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defm SH : StoreM<"sh", CPURegs, truncstorei16>, MMRel, LW_FM<0x29>;
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defm SW : StoreM<"sw", CPURegs, store>, MMRel, LW_FM<0x2b>;
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defm LB : LoadM<"lb", CPURegs, sextloadi8, IILoad>, MMRel, LW_FM<0x20>;
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defm LBu : LoadM<"lbu", CPURegs, zextloadi8, IILoad, addrDefault>, MMRel,
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LW_FM<0x24>;
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defm LH : LoadM<"lh", CPURegs, sextloadi16, IILoad, addrDefault>, MMRel,
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LW_FM<0x21>;
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defm LHu : LoadM<"lhu", CPURegs, zextloadi16, IILoad>, MMRel, LW_FM<0x25>;
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defm LW : LoadM<"lw", CPURegs, load, IILoad, addrDefault>, MMRel, LW_FM<0x23>;
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defm SB : StoreM<"sb", CPURegs, truncstorei8, IIStore>, MMRel, LW_FM<0x28>;
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defm SH : StoreM<"sh", CPURegs, truncstorei16, IIStore>, MMRel, LW_FM<0x29>;
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defm SW : StoreM<"sw", CPURegs, store, IIStore>, MMRel, LW_FM<0x2b>;
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/// load/store left/right
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defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>;
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@ -35,6 +35,9 @@ def IIFdivDouble : InstrItinClass;
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def IIFsqrtSingle : InstrItinClass;
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def IIFsqrtDouble : InstrItinClass;
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def IIFrecipFsqrtStep : InstrItinClass;
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def IIFLoad : InstrItinClass;
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def IIFStore : InstrItinClass;
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def IIFmoveC1 : InstrItinClass;
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def IIPseudo : InstrItinClass;
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//===----------------------------------------------------------------------===//
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@ -59,5 +62,8 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
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InstrItinData<IIFdivDouble , [InstrStage<36, [ALU]>]>,
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InstrItinData<IIFsqrtSingle , [InstrStage<54, [ALU]>]>,
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InstrItinData<IIFsqrtDouble , [InstrStage<12, [ALU]>]>,
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InstrItinData<IIFrecipFsqrtStep , [InstrStage<5, [ALU]>]>
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InstrItinData<IIFrecipFsqrtStep , [InstrStage<5, [ALU]>]>,
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InstrItinData<IIFLoad , [InstrStage<3, [ALU]>]>,
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InstrItinData<IIFStore , [InstrStage<1, [ALU]>]>,
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InstrItinData<IIFmoveC1 , [InstrStage<2, [ALU]>]>
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]>;
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