[mips][msa] Fix element extraction where the index is variable.
Summary: This isn't supported directly so we splat the vector element and extract the most convenient copy. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3530 llvm-svn: 207524
This commit is contained in:
Daniel Sanders
parent
aa0e88acbf
commit
b3268e71e2
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@ -3731,3 +3731,55 @@ def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64,
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MSA128D, NoItinerary>;
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def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8,
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MSA128B, NoItinerary>;
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// Vector extraction with variable index
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def : MSAPat<(i32 (vextract_sext_i8 v16i8:$ws, i32:$idx)),
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(SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
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i32:$idx),
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sub_lo)),
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GPR32), (i32 24))>;
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def : MSAPat<(i32 (vextract_sext_i16 v8i16:$ws, i32:$idx)),
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(SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
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i32:$idx),
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sub_lo)),
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GPR32), (i32 16))>;
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def : MSAPat<(i32 (vextract_sext_i32 v4i32:$ws, i32:$idx)),
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(COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
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i32:$idx),
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sub_lo)),
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GPR32)>;
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def : MSAPat<(i64 (vextract_sext_i64 v2i64:$ws, i32:$idx)),
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(COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
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i32:$idx),
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sub_64)),
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GPR64), [HasMSA, IsGP64bit]>;
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def : MSAPat<(i32 (vextract_zext_i8 v16i8:$ws, i32:$idx)),
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(SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
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i32:$idx),
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sub_lo)),
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GPR32), (i32 24))>;
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def : MSAPat<(i32 (vextract_zext_i16 v8i16:$ws, i32:$idx)),
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(SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
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i32:$idx),
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sub_lo)),
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GPR32), (i32 16))>;
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def : MSAPat<(i32 (vextract_zext_i32 v4i32:$ws, i32:$idx)),
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(COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
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i32:$idx),
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sub_lo)),
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GPR32)>;
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def : MSAPat<(i64 (vextract_zext_i64 v2i64:$ws, i32:$idx)),
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(COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
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i32:$idx),
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sub_64)),
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GPR64), [HasMSA, IsGP64bit]>;
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def : MSAPat<(f32 (vector_extract v4f32:$ws, i32:$idx)),
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(f32 (EXTRACT_SUBREG (SPLAT_W v4f32:$ws,
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i32:$idx),
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sub_lo))>;
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def : MSAPat<(f64 (vector_extract v2f64:$ws, i32:$idx)),
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(f64 (EXTRACT_SUBREG (SPLAT_D v2f64:$ws,
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i32:$idx),
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sub_64))>;
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@ -6,6 +6,7 @@
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@v8i16 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
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@v4i32 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>
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@v2i64 = global <2 x i64> <i64 0, i64 0>
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@i32 = global i32 0
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@i64 = global i64 0
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define void @const_v16i8() nounwind {
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@ -397,6 +398,198 @@ define i64 @extract_zext_v2i64() nounwind {
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; MIPS32-AE: .size extract_zext_v2i64
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}
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define i32 @extract_sext_v16i8_vidx() nounwind {
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; MIPS32-AE: extract_sext_v16i8_vidx:
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%1 = load <16 x i8>* @v16i8
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; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)(
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; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]])
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%2 = add <16 x i8> %1, %1
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; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
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%3 = load i32* @i32
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; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
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; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
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%4 = extractelement <16 x i8> %2, i32 %3
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%5 = sext i8 %4 to i32
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; MIPS32-AE-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
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; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
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; MIPS32-AE-DAG: sra [[R6:\$[0-9]+]], [[R5]], 24
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ret i32 %5
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; MIPS32-AE: .size extract_sext_v16i8_vidx
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}
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define i32 @extract_sext_v8i16_vidx() nounwind {
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; MIPS32-AE: extract_sext_v8i16_vidx:
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%1 = load <8 x i16>* @v8i16
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; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)(
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; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]])
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%2 = add <8 x i16> %1, %1
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; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
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%3 = load i32* @i32
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; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
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; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
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%4 = extractelement <8 x i16> %2, i32 %3
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%5 = sext i16 %4 to i32
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; MIPS32-AE-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
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; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
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; MIPS32-AE-DAG: sra [[R6:\$[0-9]+]], [[R5]], 16
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ret i32 %5
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; MIPS32-AE: .size extract_sext_v8i16_vidx
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}
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define i32 @extract_sext_v4i32_vidx() nounwind {
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; MIPS32-AE: extract_sext_v4i32_vidx:
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%1 = load <4 x i32>* @v4i32
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; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)(
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; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
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%2 = add <4 x i32> %1, %1
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; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
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%3 = load i32* @i32
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; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
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; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
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%4 = extractelement <4 x i32> %2, i32 %3
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; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
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; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
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; MIPS32-AE-NOT: sra
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ret i32 %4
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; MIPS32-AE: .size extract_sext_v4i32_vidx
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}
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define i64 @extract_sext_v2i64_vidx() nounwind {
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; MIPS32-AE: extract_sext_v2i64_vidx:
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%1 = load <2 x i64>* @v2i64
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; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)(
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; MIPS32-AE-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
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%2 = add <2 x i64> %1, %1
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; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
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%3 = load i32* @i32
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; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
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; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
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%4 = extractelement <2 x i64> %2, i32 %3
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; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
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; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
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; MIPS32-AE-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
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; MIPS32-AE-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]]
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; MIPS32-AE-NOT: sra
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ret i64 %4
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; MIPS32-AE: .size extract_sext_v2i64_vidx
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}
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define i32 @extract_zext_v16i8_vidx() nounwind {
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; MIPS32-AE: extract_zext_v16i8_vidx:
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%1 = load <16 x i8>* @v16i8
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; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)(
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; MIPS32-AE-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]])
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%2 = add <16 x i8> %1, %1
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; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
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%3 = load i32* @i32
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; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
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; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
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%4 = extractelement <16 x i8> %2, i32 %3
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%5 = zext i8 %4 to i32
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; MIPS32-AE-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
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; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
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; MIPS32-AE-DAG: srl [[R6:\$[0-9]+]], [[R5]], 24
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ret i32 %5
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; MIPS32-AE: .size extract_zext_v16i8_vidx
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}
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define i32 @extract_zext_v8i16_vidx() nounwind {
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; MIPS32-AE: extract_zext_v8i16_vidx:
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%1 = load <8 x i16>* @v8i16
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; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)(
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; MIPS32-AE-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]])
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%2 = add <8 x i16> %1, %1
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; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
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%3 = load i32* @i32
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; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
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; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
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%4 = extractelement <8 x i16> %2, i32 %3
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%5 = zext i16 %4 to i32
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; MIPS32-AE-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
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; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
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; MIPS32-AE-DAG: srl [[R6:\$[0-9]+]], [[R5]], 16
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ret i32 %5
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; MIPS32-AE: .size extract_zext_v8i16_vidx
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}
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define i32 @extract_zext_v4i32_vidx() nounwind {
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; MIPS32-AE: extract_zext_v4i32_vidx:
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%1 = load <4 x i32>* @v4i32
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; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)(
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; MIPS32-AE-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
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%2 = add <4 x i32> %1, %1
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; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
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%3 = load i32* @i32
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; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
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; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
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%4 = extractelement <4 x i32> %2, i32 %3
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; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
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; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
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; MIPS32-AE-NOT: srl
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ret i32 %4
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; MIPS32-AE: .size extract_zext_v4i32_vidx
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}
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define i64 @extract_zext_v2i64_vidx() nounwind {
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; MIPS32-AE: extract_zext_v2i64_vidx:
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%1 = load <2 x i64>* @v2i64
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; MIPS32-AE-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)(
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; MIPS32-AE-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
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%2 = add <2 x i64> %1, %1
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; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
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%3 = load i32* @i32
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; MIPS32-AE-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
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; MIPS32-AE-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
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%4 = extractelement <2 x i64> %2, i32 %3
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; MIPS32-AE-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
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; MIPS32-AE-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
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; MIPS32-AE-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
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; MIPS32-AE-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]]
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; MIPS32-AE-NOT: srl
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ret i64 %4
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; MIPS32-AE: .size extract_zext_v2i64_vidx
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}
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define void @insert_v16i8(i32 %a) nounwind {
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; MIPS32-AE: insert_v16i8:
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@ -3,6 +3,7 @@
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@v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>
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@v2f64 = global <2 x double> <double 0.0, double 0.0>
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@i32 = global i32 0
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@f32 = global float 0.0
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@f64 = global double 0.0
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@ -155,6 +156,27 @@ define float @extract_v4f32_elt2() nounwind {
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; MIPS32: .size extract_v4f32_elt2
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}
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define float @extract_v4f32_vidx() nounwind {
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; MIPS32: extract_v4f32_vidx:
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%1 = load <4 x float>* @v4f32
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; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)(
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; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
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%2 = fadd <4 x float> %1, %1
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; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
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%3 = load i32* @i32
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; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
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; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
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%4 = extractelement <4 x float> %2, i32 %3
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; MIPS32-DAG: splat.w $w0, [[R1]]{{\[}}[[IDX]]]
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ret float %4
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; MIPS32: .size extract_v4f32_vidx
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}
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define double @extract_v2f64() nounwind {
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; MIPS32: extract_v2f64:
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@ -199,6 +221,27 @@ define double @extract_v2f64_elt0() nounwind {
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; MIPS32: .size extract_v2f64_elt0
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}
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define double @extract_v2f64_vidx() nounwind {
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; MIPS32: extract_v2f64_vidx:
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%1 = load <2 x double>* @v2f64
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; MIPS32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)(
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; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
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%2 = fadd <2 x double> %1, %1
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; MIPS32-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
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%3 = load i32* @i32
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; MIPS32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
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; MIPS32-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
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%4 = extractelement <2 x double> %2, i32 %3
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; MIPS32-DAG: splat.d $w0, [[R1]]{{\[}}[[IDX]]]
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ret double %4
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; MIPS32: .size extract_v2f64_vidx
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}
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define void @insert_v4f32(float %a) nounwind {
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; MIPS32: insert_v4f32:
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