1. Adding test cases for MBlaze MC disassembler.
2. Fixing several errors in disassembler uncovered by test cases. 3. Fixing invalid encoding of PCMPEQ and PCMPNE uncovered by test cases. llvm-svn: 118969
This commit is contained in:
Wesley Peck
parent
2bcb8daa44
commit
b3099e6863
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@ -103,7 +103,7 @@ static unsigned decodeMUL(uint32_t insn) {
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}
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static unsigned decodeSEXT(uint32_t insn) {
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switch (getIMM(insn)) {
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switch (insn&0x7FF) {
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default: return UNSUPPORTED;
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case 0x60: return MBlaze::SEXT8;
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case 0x68: return MBlaze::WIC;
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@ -118,7 +118,7 @@ static unsigned decodeSEXT(uint32_t insn) {
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}
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static unsigned decodeBEQ(uint32_t insn) {
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switch (getRD(insn)) {
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switch ((insn>>21)&0x1F) {
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default: return UNSUPPORTED;
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case 0x00: return MBlaze::BEQ;
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case 0x10: return MBlaze::BEQD;
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@ -136,7 +136,7 @@ static unsigned decodeBEQ(uint32_t insn) {
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}
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static unsigned decodeBEQI(uint32_t insn) {
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switch (getRD(insn)) {
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switch ((insn>>21)&0x1F) {
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default: return UNSUPPORTED;
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case 0x00: return MBlaze::BEQI;
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case 0x10: return MBlaze::BEQID;
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@ -342,6 +342,22 @@ static unsigned decodeIDIV(uint32_t insn) {
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}
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}
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static unsigned decodeLBU(uint32_t insn) {
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switch ((insn>>9)&0x1) {
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default: return UNSUPPORTED;
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case 0x0: return MBlaze::LBU;
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case 0x1: return MBlaze::LBUR;
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}
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}
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static unsigned decodeLHU(uint32_t insn) {
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switch ((insn>>9)&0x1) {
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default: return UNSUPPORTED;
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case 0x0: return MBlaze::LHU;
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case 0x1: return MBlaze::LHUR;
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}
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}
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static unsigned decodeLW(uint32_t insn) {
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switch ((insn>>9)&0x3) {
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default: return UNSUPPORTED;
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@ -351,6 +367,22 @@ static unsigned decodeLW(uint32_t insn) {
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}
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}
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static unsigned decodeSB(uint32_t insn) {
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switch ((insn>>9)&0x1) {
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default: return UNSUPPORTED;
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case 0x0: return MBlaze::SB;
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case 0x1: return MBlaze::SBR;
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}
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}
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static unsigned decodeSH(uint32_t insn) {
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switch ((insn>>9)&0x1) {
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default: return UNSUPPORTED;
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case 0x0: return MBlaze::SH;
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case 0x1: return MBlaze::SHR;
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}
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}
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static unsigned decodeSW(uint32_t insn) {
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switch ((insn>>9)&0x3) {
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default: return UNSUPPORTED;
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@ -364,10 +396,10 @@ static unsigned decodeMFS(uint32_t insn) {
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switch ((insn>>15)&0x1) {
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default: return UNSUPPORTED;
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case 0x0:
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switch ((insn>>16)&0x1F) {
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switch ((insn>>16)&0x1) {
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default: return UNSUPPORTED;
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case 0x22: return MBlaze::MSRCLR;
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case 0x20: return MBlaze::MSRSET;
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case 0x0: return MBlaze::MSRSET;
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case 0x1: return MBlaze::MSRCLR;
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}
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case 0x1:
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switch ((insn>>14)&0x1) {
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@ -389,7 +421,7 @@ static unsigned decodeOR(uint32_t insn) {
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static unsigned decodeXOR(uint32_t insn) {
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switch (getFLAGS(insn)) {
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default: return UNSUPPORTED;
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case 0x000: return MBlaze::OR;
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case 0x000: return MBlaze::XOR;
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case 0x400: return MBlaze::PCMPEQ;
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}
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}
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@ -397,7 +429,7 @@ static unsigned decodeXOR(uint32_t insn) {
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static unsigned decodeANDN(uint32_t insn) {
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switch (getFLAGS(insn)) {
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default: return UNSUPPORTED;
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case 0x000: return MBlaze::OR;
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case 0x000: return MBlaze::ANDN;
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case 0x400: return MBlaze::PCMPNE;
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}
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}
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@ -428,7 +460,11 @@ static unsigned getOPCODE(uint32_t insn) {
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case MBlaze::GET: return decodeGET(insn);
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case MBlaze::GETD: return decodeGETD(insn);
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case MBlaze::IDIV: return decodeIDIV(insn);
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case MBlaze::LBU: return decodeLBU(insn);
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case MBlaze::LHU: return decodeLHU(insn);
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case MBlaze::LW: return decodeLW(insn);
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case MBlaze::SB: return decodeSB(insn);
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case MBlaze::SH: return decodeSH(insn);
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case MBlaze::SW: return decodeSW(insn);
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case MBlaze::MFS: return decodeMFS(insn);
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case MBlaze::OR: return decodeOR(insn);
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@ -455,7 +491,7 @@ bool MBlazeDisassembler::getInstruction(MCInst &instr,
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// The machine instruction.
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uint32_t insn;
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uint8_t bytes[4];
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// We want to read exactly 4 bytes of data.
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if (region.readBytes(address, 4, (uint8_t*)bytes, NULL) == -1)
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return false;
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@ -475,16 +511,50 @@ bool MBlazeDisassembler::getInstruction(MCInst &instr,
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switch ((tsFlags & MBlazeII::FormMask)) {
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default: llvm_unreachable("unknown instruction encoding");
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case MBlazeII::FRRRR:
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instr.addOperand(MCOperand::CreateReg(getRD(insn)));
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instr.addOperand(MCOperand::CreateReg(getRB(insn)));
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instr.addOperand(MCOperand::CreateReg(getRA(insn)));
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break;
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case MBlazeII::FRRR:
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instr.addOperand(MCOperand::CreateReg(getRD(insn)));
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instr.addOperand(MCOperand::CreateReg(getRA(insn)));
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instr.addOperand(MCOperand::CreateReg(getRB(insn)));
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break;
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case MBlazeII::FRI:
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switch (opcode) {
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default: llvm_unreachable("unknown instruction encoding");
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case MBlaze::MFS:
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instr.addOperand(MCOperand::CreateReg(getRD(insn)));
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instr.addOperand(MCOperand::CreateImm(insn&0x3FFF));
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break;
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case MBlaze::MTS:
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instr.addOperand(MCOperand::CreateImm(insn&0x3FFF));
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instr.addOperand(MCOperand::CreateReg(getRA(insn)));
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break;
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case MBlaze::MSRSET:
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case MBlaze::MSRCLR:
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instr.addOperand(MCOperand::CreateReg(getRD(insn)));
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instr.addOperand(MCOperand::CreateImm(insn&0x7FFF));
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break;
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}
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break;
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case MBlazeII::FRRI:
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instr.addOperand(MCOperand::CreateReg(getRD(insn)));
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instr.addOperand(MCOperand::CreateReg(getRA(insn)));
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instr.addOperand(MCOperand::CreateImm(getIMM(insn)));
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switch (opcode) {
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default:
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instr.addOperand(MCOperand::CreateImm(getIMM(insn)));
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break;
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case MBlaze::BSRLI:
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case MBlaze::BSRAI:
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case MBlaze::BSLLI:
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instr.addOperand(MCOperand::CreateImm(insn&0x1F));
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break;
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}
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break;
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case MBlazeII::FCRR:
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@ -568,8 +638,8 @@ static MCDisassembler *createMBlazeDisassembler(const Target &T) {
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return new MBlazeDisassembler;
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}
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extern "C" void LLVMInitializeMBlazeDisassembler() {
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extern "C" void LLVMInitializeMBlazeDisassembler() {
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// Register the disassembler.
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TargetRegistry::RegisterMCDisassembler(TheMBlazeTarget,
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TargetRegistry::RegisterMCDisassembler(TheMBlazeTarget,
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createMBlazeDisassembler);
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}
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@ -325,8 +325,8 @@ let isCommutable = 1, isAsCheapAsAMove = 1 in {
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def OR : Logic<0x20, 0x000, "or ", or>;
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def XOR : Logic<0x22, 0x000, "xor ", xor>;
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def PCMPBF : PatCmp<0x20, 0x400, "pcmpbf ">;
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def PCMPEQ : PatCmp<0x23, 0x400, "pcmpeq ">;
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def PCMPNE : PatCmp<0x22, 0x400, "pcmpne ">;
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def PCMPEQ : PatCmp<0x22, 0x400, "pcmpeq ">;
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def PCMPNE : PatCmp<0x23, 0x400, "pcmpne ">;
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}
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let isAsCheapAsAMove = 1 in {
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@ -37,3 +37,6 @@
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- The assembly parser does not use any MicroBlaze specific directives.
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I should investigate if there are MicroBlaze specific directive and,
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if there are, add them.
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- The instruction MFS and MTS use special names for some of the
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special registers that can be accessed. These special register
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names should be parsed by the assembly parser.
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@ -11,12 +11,12 @@
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# CHECK: encoding: [0x80,0x01,0x14,0x00]
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pcmpbf r0, r1, r2
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# CHECK: pcmpeq
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# CHECK: pcmpne
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# BINARY: 100011 00000 00001 00010 10000000000
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# CHECK: encoding: [0x8c,0x01,0x14,0x00]
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pcmpeq r0, r1, r2
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pcmpne r0, r1, r2
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# CHECK: pcmpne
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# CHECK: pcmpeq
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# BINARY: 100010 00000 00001 00010 10000000000
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# CHECK: encoding: [0x88,0x01,0x14,0x00]
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pcmpne r0, r1, r2
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pcmpeq r0, r1, r2
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