[RISCV] Add stub backend
This contains just enough for lib/Target/RISCV to compile. Notably a basic RISCVTargetMachine and RISCVTargetInfo. At this point you can attempt llc -march=riscv32 myinput.ll and will find it fails due to the lack of MCAsmInfo. See http://lists.llvm.org/pipermail/llvm-dev/2016-August/103748.html for further discussion Differential Revision: https://reviews.llvm.org/D23560 llvm-svn: 285712
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@ -279,6 +279,7 @@ set(LLVM_ALL_TARGETS
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MSP430
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NVPTX
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PowerPC
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RISCV
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Sparc
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SystemZ
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X86
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@ -17,6 +17,10 @@ E: mail@justinbogner.com
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D: InstrProfiling and related parts of ProfileData
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D: SelectionDAG (lib/CodeGen/SelectionDAG/*)
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N: Alex Bradbury
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E: asb@lowrisc.org
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D: RISC-V backend (lib/Target/RISCV/*)
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N: Chandler Carruth
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E: chandlerc@gmail.com
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E: chandlerc@google.com
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@ -83,6 +83,10 @@ AMDGPU
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* `AMD Compute Resources <http://developer.amd.com/tools/heterogeneous-computing/amd-accelerated-parallel-processing-app-sdk/documentation/>`_
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* `AMDGPU Compute Application Binary Interface <https://github.com/RadeonOpenCompute/ROCm-ComputeABI-Doc/blob/master/AMDGPU-ABI.md>`__
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RISC-V
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------
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* `RISC-V User-Level ISA Specification <https://riscv.org/specifications/>`_
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SPARC
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-----
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@ -30,6 +30,7 @@ subdirectories =
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NVPTX
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Mips
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PowerPC
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RISCV
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Sparc
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SystemZ
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WebAssembly
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@ -0,0 +1,5 @@
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add_llvm_target(RISCVCodeGen
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RISCVTargetMachine.cpp
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)
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add_subdirectory(TargetInfo)
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@ -0,0 +1,31 @@
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;===- ./lib/Target/RISCV/LLVMBuild.txt -------------------------*- Conf -*--===;
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;
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; The LLVM Compiler Infrastructure
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;
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; This file is distributed under the University of Illinois Open Source
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; License. See LICENSE.TXT for details.
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;
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;===------------------------------------------------------------------------===;
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;
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; This is an LLVMBuild description file for the components in this subdirectory.
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;
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; For more information on the LLVMBuild system, please see:
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;
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; http://llvm.org/docs/LLVMBuild.html
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;
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;===------------------------------------------------------------------------===;
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[common]
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subdirectories = TargetInfo
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[component_0]
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type = TargetGroup
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name = RISCV
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parent = Target
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[component_1]
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type = Library
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name = RISCVCodeGen
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parent = RISCV
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required_libraries = Core CodeGen RISCVInfo Support Target
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add_to_library_groups = RISCV
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@ -0,0 +1,58 @@
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//===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about RISCV target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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extern "C" void LLVMInitializeRISCVTarget() {
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RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
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RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
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}
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static std::string computeDataLayout(const Triple &TT) {
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if (TT.isArch64Bit()) {
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return "e-m:e-i64:64-n32:64-S128";
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} else {
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assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
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return "e-m:e-i64:64-n32-S128";
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}
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}
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static Reloc::Model getEffectiveRelocModel(const Triple &TT,
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Optional<Reloc::Model> RM) {
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if (!RM.hasValue())
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return Reloc::Static;
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return *RM;
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}
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RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Optional<Reloc::Model> RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
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getEffectiveRelocModel(TT, RM), CM, OL),
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TLOF(make_unique<TargetLoweringObjectFileELF>()) {}
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TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new TargetPassConfig(this, PM);
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}
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@ -0,0 +1,41 @@
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//===-- RISCVTargetMachine.h - Define TargetMachine for RISCV ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the RISCV specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVTARGETMACHINE_H
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#define LLVM_LIB_TARGET_RISCV_RISCVTARGETMACHINE_H
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#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/IR/DataLayout.h"
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namespace llvm {
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class RISCVTargetMachine : public LLVMTargetMachine {
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std::unique_ptr<TargetLoweringObjectFile> TLOF;
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public:
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RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Optional<Reloc::Model> RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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TargetLoweringObjectFile *getObjFileLowering() const override {
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return TLOF.get();
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}
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};
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Target &getTheRISCV32Target();
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Target &getTheRISCV64Target();
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}
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#endif
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@ -0,0 +1,3 @@
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add_llvm_library(LLVMRISCVInfo
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RISCVTargetInfo.cpp
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)
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@ -0,0 +1,23 @@
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;===- ./lib/Target/RISCV/TargetInfo/LLVMBuild.txt --------------*- Conf -*--===;
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;
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; The LLVM Compiler Infrastructure
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;
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; This file is distributed under the University of Illinois Open Source
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; License. See LICENSE.TXT for details.
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;
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;===------------------------------------------------------------------------===;
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;
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; This is an LLVMBuild description file for the components in this subdirectory.
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;
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; For more information on the LLVMBuild system, please see:
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;
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; http://llvm.org/docs/LLVMBuild.html
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;
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;===------------------------------------------------------------------------===;
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[component_0]
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type = Library
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name = RISCVInfo
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parent = RISCV
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required_libraries = Support
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add_to_library_groups = RISCV
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@ -0,0 +1,35 @@
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//===-- RISCVTargetInfo.cpp - RISCV Target Implementation -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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namespace llvm {
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Target &getTheRISCV32Target() {
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static Target TheRISCV32Target;
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return TheRISCV32Target;
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}
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Target &getTheRISCV64Target() {
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static Target TheRISCV64Target;
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return TheRISCV64Target;
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}
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}
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extern "C" void LLVMInitializeRISCVTargetInfo() {
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RegisterTarget<Triple::riscv32> X(getTheRISCV32Target(), "riscv32",
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"32-bit RISC-V");
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RegisterTarget<Triple::riscv64> Y(getTheRISCV64Target(), "riscv64",
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"64-bit RISC-V");
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}
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// FIXME: Temporary stub - this function must be defined for linking
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// to succeed and will be called unconditionally by llc, so must be a no-op.
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// Remove once this function is properly implemented.
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extern "C" void LLVMInitializeRISCVTargetMC() {}
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