[mips] Add preliminary support for the MIPS II target.
Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
This commit is contained in:
Vasileios Kalintiris
parent
8c1c95e95c
commit
b2dd15f8c7
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@ -1653,6 +1653,12 @@ let AdditionalPredicates = [NotDSP] in {
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(ADDiu GPR32:$src, imm:$imm)>;
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}
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// Support multiplication for pre-Mips32 targets that don't have
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// the MUL instruction.
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def : MipsPat<(mul GPR32:$lhs, GPR32:$rhs),
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(PseudoMFLO (PseudoMULT GPR32:$lhs, GPR32:$rhs))>,
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ISA_MIPS1_NOT_32R6_64R6;
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// SYNC
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def : MipsPat<(MipsSync (i32 immz)),
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(SYNC 0)>, ISA_MIPS2;
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@ -109,7 +109,7 @@ static std::string computeDataLayout(const MipsSubtarget &ST) {
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MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
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const std::string &FS, bool little,
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const MipsTargetMachine *_TM)
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: MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32),
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: MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
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ABI(MipsABIInfo::Unknown()), IsLittle(little), IsSingleFloat(false),
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IsFPXX(false), NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
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IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
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@ -126,13 +126,14 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
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PreviousInMips16Mode = InMips16Mode;
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// Don't even attempt to generate code for MIPS-I, MIPS-II, MIPS-III, and
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// MIPS-V. They have not been tested and currently exist for the integrated
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if (MipsArchVersion == MipsDefault)
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MipsArchVersion = Mips32;
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// Don't even attempt to generate code for MIPS-I, MIPS-III and MIPS-V.
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// They have not been tested and currently exist for the integrated
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// assembler only.
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if (MipsArchVersion == Mips1)
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report_fatal_error("Code generation for MIPS-I is not implemented", false);
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if (MipsArchVersion == Mips2)
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report_fatal_error("Code generation for MIPS-II is not implemented", false);
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if (MipsArchVersion == Mips3)
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report_fatal_error("Code generation for MIPS-III is not implemented",
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false);
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@ -37,6 +37,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
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virtual void anchor();
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enum MipsArchEnum {
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MipsDefault,
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Mips1, Mips2, Mips32, Mips32r2, Mips32r6, Mips3, Mips4, Mips5, Mips64,
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Mips64r2, Mips64r6
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};
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@ -0,0 +1,181 @@
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; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=M2
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; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=32R1-R2 -check-prefix=32R1
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; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=32R1-R2 -check-prefix=32R2
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; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=32R6
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; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=M4
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; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=64R1-R2
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; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=64R1-R2
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; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=64R6
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define signext i1 @mul_i1(i1 signext %a, i1 signext %b) {
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entry:
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; ALL-LABEL: mul_i1:
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; M2: mult $4, $5
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; M2: mflo $[[T0:[0-9]+]]
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; M2: sll $[[T0]], $[[T0]], 31
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; M2: sra $2, $[[T0]], 31
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; 32R1-R2: mul $[[T0:[0-9]+]], $4, $5
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; 32R1-R2: sll $[[T0]], $[[T0]], 31
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; 32R1-R2: sra $2, $[[T0]], 31
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; 32R6: mul $[[T0:[0-9]+]], $4, $5
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; 32R6: sll $[[T0]], $[[T0]], 31
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; 32R6: sra $2, $[[T0]], 31
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; M4: mult $4, $5
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; M4: mflo $[[T0:[0-9]+]]
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; M4: sll $[[T0]], $[[T0]], 31
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; M4: sra $2, $[[T0]], 31
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; 64R1-R2: mul $[[T0:[0-9]+]], $4, $5
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; 64R1-R2: sll $[[T0]], $[[T0]], 31
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; 64R1-R2: sra $2, $[[T0]], 31
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; 64R6: mul $[[T0:[0-9]+]], $4, $5
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; 64R6: sll $[[T0]], $[[T0]], 31
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; 64R6: sra $2, $[[T0]], 31
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%r = mul i1 %a, %b
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ret i1 %r
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}
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define signext i8 @mul_i8(i8 signext %a, i8 signext %b) {
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entry:
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; ALL-LABEL: mul_i8:
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; M2: mult $4, $5
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; M2: mflo $[[T0:[0-9]+]]
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; M2: sll $[[T0]], $[[T0]], 24
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; M2: sra $2, $[[T0]], 24
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; 32R1: mul $[[T0:[0-9]+]], $4, $5
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; 32R1: sll $[[T0]], $[[T0]], 24
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; 32R1: sra $2, $[[T0]], 24
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; 32R2: mul $[[T0:[0-9]+]], $4, $5
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; 32R2: seb $2, $[[T0]]
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; 32R6: mul $[[T0:[0-9]+]], $4, $5
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; 32R6: seb $2, $[[T0]]
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; M4: mult $4, $5
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; M4: mflo $[[T0:[0-9]+]]
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; M4: sll $[[T0]], $[[T0]], 24
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; M4: sra $2, $[[T0]], 24
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; 64R1: mul $[[T0:[0-9]+]], $4, $5
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; 64R1: sll $[[T0]], $[[T0]], 24
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; 64R1: sra $2, $[[T0]], 24
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; 64R2: mul $[[T0:[0-9]+]], $4, $5
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; 64R2: seb $2, $[[T0]]
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; 64R6: mul $[[T0:[0-9]+]], $4, $5
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; 64R6: seb $2, $[[T0]]
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%r = mul i8 %a, %b
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ret i8 %r
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}
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define signext i16 @mul_i16(i16 signext %a, i16 signext %b) {
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entry:
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; ALL-LABEL: mul_i16:
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; M2: mult $4, $5
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; M2: mflo $[[T0:[0-9]+]]
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; M2: sll $[[T0]], $[[T0]], 16
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; M2: sra $2, $[[T0]], 16
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; 32R1: mul $[[T0:[0-9]+]], $4, $5
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; 32R1: sll $[[T0]], $[[T0]], 16
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; 32R1: sra $2, $[[T0]], 16
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; 32R2: mul $[[T0:[0-9]+]], $4, $5
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; 32R2: seh $2, $[[T0]]
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; 32R6: mul $[[T0:[0-9]+]], $4, $5
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; 32R6: seh $2, $[[T0]]
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; M4: mult $4, $5
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; M4: mflo $[[T0:[0-9]+]]
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; M4: sll $[[T0]], $[[T0]], 16
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; M4: sra $2, $[[T0]], 16
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; 64R1: mul $[[T0:[0-9]+]], $4, $5
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; 64R1: sll $[[T0]], $[[T0]], 16
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; 64R1: sra $2, $[[T0]], 16
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; 64R2: mul $[[T0:[0-9]+]], $4, $5
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; 64R2: seh $2, $[[T0]]
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; 64R6: mul $[[T0:[0-9]+]], $4, $5
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; 64R6: seh $2, $[[T0]]
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%r = mul i16 %a, %b
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ret i16 %r
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}
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define signext i32 @mul_i32(i32 signext %a, i32 signext %b) {
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entry:
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; ALL-LABEL: mul_i32:
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; M2: mult $4, $5
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; M2: mflo $2
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; 32R1-R2: mul $2, $4, $5
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; 32R6: mul $2, $4, $5
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; 64R1-R2: mul $2, $4, $5
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; 64R6: mul $2, $4, $5
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%r = mul i32 %a, %b
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ret i32 %r
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}
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define signext i64 @mul_i64(i64 signext %a, i64 signext %b) {
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entry:
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; ALL-LABEL: mul_i64:
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; M2: mult $4, $7
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; M2: mflo $[[T0:[0-9]+]]
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; M2: mult $5, $6
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; M2: mflo $[[T1:[0-9]+]]
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; M2: multu $5, $7
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; M2: mflo $3
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; M2: mfhi $4
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; M2: addu $[[T2:[0-9]+]], $4, $[[T1]]
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; M2: addu $2, $[[T2]], $[[T0]]
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; 32R1-R2: multu $5, $7
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; 32R1-R2: mflo $3
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; 32R1-R2: mfhi $[[T0:[0-9]+]]
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; 32R1-R2: mul $[[T1:[0-9]+]], $4, $7
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; 32R1-R2: mul $[[T2:[0-9]+]], $5, $6
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; 32R1-R2: addu $[[T0]], $[[T0]], $[[T2:[0-9]+]]
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; 32R1-R2: addu $2, $[[T0]], $[[T1]]
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; 32R6: mul $[[T0:[0-9]+]], $5, $6
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; 32R6: muhu $[[T1:[0-9]+]], $5, $7
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; 32R6: addu $[[T0]], $[[T1]], $[[T0]]
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; 32R6: mul $[[T2:[0-9]+]], $4, $7
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; 32R6: addu $2, $[[T0]], $[[T2]]
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; 32R6: mul $3, $5, $7
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; M4: dmult $4, $5
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; M4: mflo $2
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; 64R1-R2: dmult $4, $5
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; 64R1-R2: mflo $2
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; 64R6: dmul $2, $4, $5
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%r = mul i64 %a, %b
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ret i64 %r
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}
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