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Converted an overly aggressive assert to a conditional check in AddCombineTo64bitMLAL. 

Said assert assumes that ADDC will always have a glue node as its second
argument and is checked before we even know that we are actually performing the
relevant MLAL optimization. This is incorrect since on ARM we *CAN* codegen ADDC
with a use list based second argument. Thus to have both effects, I converted
the assert to a conditional check which if it fails we do not perform the
optimization.

In terms of tests I can not produce an ADDC from the IR level until I get in my
multiprecision optimization patch which is forthcoming. The tests for said patch
would cause this assert to fail implying that said tests will provide the
relevant tests.

llvm-svn: 184230
This commit is contained in:
Michael Gottesman 2013-06-18 20:49:40 +00:00
parent 3025f2366f
commit b2a70564a7
1 changed files with 5 additions and 2 deletions
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7
llvm/lib/Target/ARM/ARMISelLowering.cpp
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@ -7948,8 +7948,11 @@ static SDValue AddCombineTo64bitMLAL(SDNode *AddcNode,
assert(AddcNode->getNumValues() == 2 &&
AddcNode->getValueType(0) == MVT::i32 &&
AddcNode->getValueType(1) == MVT::Glue &&
"Expect ADDC with two result values: i32, glue");
"Expect ADDC with two result values. First: i32");
// Check that we have a glued ADDC node.
if (AddcNode->getValueType(1) != MVT::Glue)
return SDValue();
// Check that the ADDC adds the low result of the S/UMUL_LOHI.
if (AddcOp0->getOpcode() != ISD::UMUL_LOHI &&