Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
llvm-svn: 150878
This commit is contained in:
Jia Liu
parent
26538e8cc5
commit
b22310fda6
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//===-- ARM.h - Top-level interface for ARM representation---- --*- C++ -*-===//
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//===-- ARM.h - Top-level interface for ARM representation-------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===- ARM.td - Describe the ARM Target Machine ------------*- tablegen -*-===//
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//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===-- ARMAsmPrinter.h - Print machine code to an ARM .s file ------------===//
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//===-- ARMAsmPrinter.h - Print machine code to an ARM .s file --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
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//===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
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//===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
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//===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===- ARMBaseRegisterInfo.h - ARM Register Information Impl ----*- C++ -*-===//
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//===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===-------- ARMBuildAttrs.h - ARM Build Attributes ------------*- C++ -*-===//
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//===-- ARMBuildAttrs.h - ARM Build Attributes ------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===-- ARMCallingConv.h - ARM Custom Calling Convention Routines ---------===//
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//=== ARMCallingConv.h - ARM Custom Calling Convention Routines -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===- ARMCallingConv.td - Calling Conventions for ARM -----*- tablegen -*-===//
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//===-- ARMCallingConv.td - Calling Conventions for ARM ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===- ARMConstantPoolValue.cpp - ARM constantpool value --------*- C++ -*-===//
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//===-- ARMConstantPoolValue.cpp - ARM constantpool value -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===- ARMConstantPoolValue.h - ARM constantpool value ----------*- C++ -*-===//
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//===-- ARMConstantPoolValue.h - ARM constantpool value ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -----*- C++ -*-=//
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//===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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//=======- ARMFrameLowering.cpp - ARM Frame Information --------*- C++ -*-====//
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//===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=//
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//===-- ARMInstrFormats.td - ARM Instruction Formats -------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
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//===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===//
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//===-- ARMInstrInfo.h - ARM Instruction Information ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
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//===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
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//===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
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//===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===- ARMInstrVFP.td - VFP support for ARM ----------------*- tablegen -*-===//
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//===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===- ARMJITInfo.h - ARM implementation of the JIT interface --*- C++ -*-===//
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//===-- ARMJITInfo.h - ARM implementation of the JIT interface -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===-- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass ----*- C++ -*-=//
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//===-- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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//====- ARMMachineFuctionInfo.cpp - ARM machine function info ---*- C++ -*-===//
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//===-- ARMMachineFuctionInfo.cpp - ARM machine function info -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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//====- ARMMachineFuctionInfo.h - ARM machine function info -----*- C++ -*-===//
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//===-- ARMMachineFuctionInfo.h - ARM machine function info -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===-- ARMPerfectShuffle.h - NEON Perfect Shuffle Table ------------------===//
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//===-- ARMPerfectShuffle.h - NEON Perfect Shuffle Table --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
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//===-- ARMRegisterInfo.cpp - ARM Register Information --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===- ARMRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===//
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//===-- ARMRegisterInfo.h - ARM Register Information Impl -------*- C++ -*-===//
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//
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//
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//===- ARMRegisterInfo.td - ARM Register defs --------------*- tablegen -*-===//
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//===-- ARMRegisterInfo.td - ARM Register defs -------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===- ARMRelocations.h - ARM Code Relocations ------------------*- C++ -*-===//
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//===-- ARMRelocations.h - ARM Code Relocations -----------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===- ARMSchedule.td - ARM Scheduling Definitions ---------*- tablegen -*-===//
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//
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//===-- ARMSchedule.td - ARM Scheduling Definitions --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//===- ARMScheduleV6.td - ARM v6 Scheduling Definitions ----*- tablegen -*-===//
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//
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//===-- ARMScheduleV6.td - ARM v6 Scheduling Definitions ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the ARM v6 processors.
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//===-- ARMSubtarget.cpp - ARM Subtarget Information ------------*- C++ -*-===//
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//===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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//=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
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//===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
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//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===-- ARMInstPrinter.h - Convert ARM MCInst to assembly syntax ----------===//
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//===- ARMInstPrinter.h - Convert ARM MCInst to assembly syntax -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===- ARMAddressingModes.h - ARM Addressing Modes --------------*- C++ -*-===//
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//===-- ARMAddressingModes.h - ARM Addressing Modes -------------*- C++ -*-===//
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//
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//
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//===-- ARMMCAsmInfo.cpp - ARM asm properties -------------------*- C++ -*-===//
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//===-- ARMMCAsmInfo.cpp - ARM asm properties -----------------------------===//
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//
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//
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//=====-- ARMMCAsmInfo.h - ARM asm properties -------------*- C++ -*--====//
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//===-- ARMMCAsmInfo.h - ARM asm properties --------------------*- C++ -*--===//
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//
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//
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//===-- ARMMCExpr.h - ARM specific MC expression classes ------------------===//
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//===-- ARMMCExpr.h - ARM specific MC expression classes --------*- C++ -*-===//
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//
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//
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//===-- ARMMCTargetDesc.cpp - ARM Target Descriptions -----------*- C++ -*-===//
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//===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===-- MLxExpansionPass.cpp - Expand MLx instrs to avoid hazards ----------=//
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//===-- MLxExpansionPass.cpp - Expand MLx instrs to avoid hazards ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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//======- Thumb1FrameLowering.cpp - Thumb1 Frame Information ---*- C++ -*-====//
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//===-- Thumb1FrameLowering.cpp - Thumb1 Frame Information ----------------===//
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//
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//
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//===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===//
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//===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===//
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//
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//===- Thumb1InstrInfo.h - Thumb-1 Instruction Information ------*- C++ -*-===//
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//===-- Thumb1InstrInfo.h - Thumb-1 Instruction Information -----*- C++ -*-===//
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//
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//
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//===- Thumb1RegisterInfo.cpp - Thumb-1 Register Information ----*- C++ -*-===//
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//===-- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===-- Thumb2ITBlockPass.cpp - Insert Thumb IT blocks ----------*- C++ -*-===//
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//===-- Thumb2ITBlockPass.cpp - Insert Thumb-2 IT blocks ------------------===//
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//
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//
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//===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
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//===-- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information -------------===//
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//
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//
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//===- Thumb2InstrInfo.h - Thumb-2 Instruction Information ------*- C++ -*-===//
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//===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===//
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//
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//
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//===- Thumb2RegisterInfo.cpp - Thumb-2 Register Information ----*- C++ -*-===//
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//===-- Thumb2RegisterInfo.cpp - Thumb-2 Register Information -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===-- CellSDKIntrinsics.td - Cell SDK Intrinsics ---------*- tablegen -*-===//
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//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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//===-- SPUMCTargetDesc.cpp - Cell SPU Target Descriptions -----*- C++ -*-===//
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//===-- SPUMCTargetDesc.cpp - Cell SPU Target Descriptions ----------------===//
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// The LLVM Compiler Infrastructure
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//
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//===-- SPU.h - Top-level interface for Cell SPU Target ----------*- C++ -*-==//
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//===-- SPU.h - Top-level interface for Cell SPU Target ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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//===- SPU.td - Describe the STI Cell SPU Target Machine ----*- tablegen -*-===//
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//
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//===-- SPU.td - Describe the STI Cell SPU Target Machine --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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//===--- SPU128InstrInfo.td - Cell SPU 128-bit operations -*- tablegen -*--===//
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//===-- SPU128InstrInfo.td - Cell SPU 128-bit operations --*- tablegen -*--===//
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//
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// Cell SPU 128-bit operations
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//
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//===----------------------------------------------------------------------===//
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// zext 32->128: Zero extend 32-bit to 128-bit
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def : Pat<(i128 (zext R32C:$rSrc)),
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(ROTQMBYIr128_zext_r32 R32C:$rSrc, 12)>;
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//====--- SPU64InstrInfo.td - Cell SPU 64-bit operations -*- tablegen -*--====//
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//====-- SPU64InstrInfo.td - Cell SPU 64-bit operations ---*- tablegen -*--===//
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//
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// Cell SPU 64-bit operations
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//
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//===-- SPUAsmPrinter.cpp - Print machine instrs to Cell SPU assembly -------=//
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//===-- SPUAsmPrinter.cpp - Print machine instrs to Cell SPU assembly -----===//
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//
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// The LLVM Compiler Infrastructure
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//
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
//===- SPUCallingConv.td - Calling Conventions for CellSPU -*- tablegen -*-===//
|
||||
//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This describes the calling conventions for the STI Cell SPU architecture.
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//=====-- SPUFrameLowering.h - SPU Frame Lowering stuff -*- C++ -*----========//
|
||||
//===-- SPUFrameLowering.h - SPU Frame Lowering stuff ----------*- C++ -*--===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//==-- SPUInstrBuilder.h - Aides for building Cell SPU insts -----*- C++ -*-==//
|
||||
//===-- SPUInstrBuilder.h - Aides for building Cell SPU insts ---*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
//==== SPUInstrFormats.td - Cell SPU Instruction Formats ---*- tablegen -*-===//
|
||||
//
|
||||
//===-- SPUInstrFormats.td - Cell SPU Instruction Formats --*- tablegen -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
|
||||
//===-- SPUInstrInfo.cpp - Cell SPU Instruction Information ---------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===- SPUInstrInfo.h - Cell SPU Instruction Information --------*- C++ -*-===//
|
||||
//===-- SPUInstrInfo.h - Cell SPU Instruction Information -------*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//==-- SPUMachineFunctionInfo.cpp - Private data used for CellSPU -*- C++ -*-=//
|
||||
//==-- SPUMachineFunctionInfo.cpp - Private data used for CellSPU ---------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//======--- SPUMathInst.td - Cell SPU math operations -*- tablegen -*---======//
|
||||
//===-- SPUMathInst.td - Cell SPU math operations ---------*- tablegen -*--===//
|
||||
//
|
||||
// Cell SPU math operations
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===- SPUNodes.td - Specialized SelectionDAG nodes used for CellSPU ------===//
|
||||
//=== SPUNodes.td - Specialized SelectionDAG nodes by CellSPU -*- tablegen -*-//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===-- SPUNopFiller.cpp - Add nops/lnops to align the pipelines---===//
|
||||
//===-- SPUNopFiller.cpp - Add nops/lnops to align the pipelines ----------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
//===- SPUOperands.td - Cell SPU Instruction Operands ------*- tablegen -*-===//
|
||||
//
|
||||
//===-- SPUOperands.td - Cell SPU Instruction Operands -----*- tablegen -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Cell SPU Instruction Operands:
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===- SPURegisterInfo.cpp - Cell SPU Register Information ----------------===//
|
||||
//===-- SPURegisterInfo.cpp - Cell SPU Register Information ---------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===- SPURegisterInfo.h - Cell SPU Register Information Impl ----*- C++ -*-==//
|
||||
//===-- SPURegisterInfo.h - Cell SPU Register Information Impl --*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
//===- SPURegisterInfo.td - The Cell SPU Register File -----*- tablegen -*-===//
|
||||
//
|
||||
//===-- SPURegisterInfo.td - The Cell SPU Register File ----*- tablegen -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
//===- SPUSchedule.td - Cell Scheduling Definitions --------*- tablegen -*-===//
|
||||
//
|
||||
//===-- SPUSchedule.td - Cell Scheduling Definitions -------*- tablegen -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===- SPUSubtarget.cpp - STI Cell SPU Subtarget Information --------------===//
|
||||
//===-- SPUSubtarget.cpp - STI Cell SPU Subtarget Information -------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===-- SPUTargetMachine.h - Define TargetMachine for Cell SPU ----*- C++ -*-=//
|
||||
//===-- SPUTargetMachine.h - Define TargetMachine for Cell SPU --*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===- Hexagon.td - Describe the Hexagon Target Machine ---------*- C++ -*-===//
|
||||
//===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
@ -7,6 +7,7 @@
|
|||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This is the top level entry point for the Hexagon target.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
|
|
@ -18,8 +19,7 @@ include "llvm/Target/Target.td"
|
|||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Hexagon Subtarget features.
|
||||
//
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Hexagon Archtectures
|
||||
def ArchV2 : SubtargetFeature<"v2", "HexagonArchVersion", "V2",
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===-- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly ----=//
|
||||
//===-- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly --===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===---- HexagonCFGOptimizer.cpp - CFG optimizations ---------------------===//
|
||||
//===-- HexagonCFGOptimizer.cpp - CFG optimizations -----------------------===//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
//===- HexagonExpandPredSpillCode.cpp - Expand Predicate Spill Code -------===//
|
||||
//===-- HexagonExpandPredSpillCode.cpp - Expand Predicate Spill Code ------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===////
|
||||
//===----------------------------------------------------------------------===//
|
||||
// The Hexagon processor has no instructions that load or store predicate
|
||||
// registers directly. So, when these registers must be spilled a general
|
||||
// purpose register must be found and the value copied to/from it from/to
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===- HexagonFrameLowering.cpp - Define frame lowering -------------------===//
|
||||
//===-- HexagonFrameLowering.cpp - Define frame lowering ------------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//==-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon ----==//
|
||||
//===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//==-- HexagonISelLowering.h - Hexagon DAG Lowering Interface ----*- C++ -*-==//
|
||||
//===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//=- HexagonImmediates.td - Hexagon immediate processing --*- tablegen -*-=//
|
||||
//===- HexagonImmediates.td - Hexagon immediate processing -*- tablegen -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -7,16 +7,16 @@
|
|||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//----------------------------------------------------------------------------//
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Hexagon Intruction Flags +
|
||||
//
|
||||
// *** Must match HexagonBaseInfo.h ***
|
||||
//----------------------------------------------------------------------------//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
|
||||
//----------------------------------------------------------------------------//
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Intruction Class Declaration +
|
||||
//----------------------------------------------------------------------------//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||
string cstr, InstrItinClass itin> : Instruction {
|
||||
|
|
@ -40,9 +40,9 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
|
|||
// *** The code above must match HexagonBaseInfo.h ***
|
||||
}
|
||||
|
||||
//----------------------------------------------------------------------------//
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Intruction Classes Definitions +
|
||||
//----------------------------------------------------------------------------//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// LD Instruction Class in V2/V3/V4.
|
||||
// Definition of the instruction class NOT CHANGED.
|
||||
|
|
@ -188,9 +188,9 @@ class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|||
: InstHexagon<outs, ins, asmstr, pattern, "", PSEUDO>;
|
||||
|
||||
|
||||
//----------------------------------------------------------------------------//
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Intruction Classes Definitions -
|
||||
//----------------------------------------------------------------------------//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
|
||||
//===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//=- HexagonInstrInfo.h - Hexagon Instruction Information ---------*- C++ -*-=//
|
||||
//===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===- HexagonIntrinsics.td - Instruction intrinsics -------*- tablegen -*-===//
|
||||
//===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===- HexagonRegisterInfo.cpp - Hexagon Register Information -------------===//
|
||||
//===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===- HexagonRegisterInfo.td - Hexagon Register defs ------*- tablegen -*-===//
|
||||
//===-- HexagonRegisterInfo.td - Hexagon Register defs -----*- tablegen -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===-HexagonSchedule.td - Hexagon Scheduling Definitions -------*- C++ -*-===//
|
||||
//===- HexagonSchedule.td - Hexagon Scheduling Definitions -*- tablegen -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//=-HexagoSelectCCInfo.td - Selectcc mappings ----------------*- tablegen -*-=//
|
||||
//===-- HexagoSelectCCInfo.td - Selectcc mappings ----------*- tablegen -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//=-- HexagonSelectionDAGInfo.h - Hexagon SelectionDAG Info ------*- C++ -*-=//
|
||||
//===-- HexagonSelectionDAGInfo.h - Hexagon SelectionDAG Info ---*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===---- HexagonSplitTFRCondSets.cpp - split TFR condsets into xfers -----===//
|
||||
//===-- HexagonSplitTFRCondSets.cpp - split TFR condsets into xfers -------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
@ -6,7 +6,7 @@
|
|||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===////
|
||||
//===----------------------------------------------------------------------===//
|
||||
// This pass tries to provide opportunities for better optimization of muxes.
|
||||
// The default code generated for something like: flag = (a == b) ? 1 : 3;
|
||||
// would be:
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===- HexagonSubtarget.cpp - Hexagon Subtarget Information ---------------===//
|
||||
//===-- HexagonSubtarget.cpp - Hexagon Subtarget Information --------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//==-- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-==//
|
||||
//===-- HexagonSubtarget.h - Define Subtarget for the Hexagon ---*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon --------===//
|
||||
//===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
@ -7,6 +7,7 @@
|
|||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// Implements the info about Hexagon target spec.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===-- HexagonTargetObjectFile.cpp - Hexagon asm properties ----*- C++ -*-===//
|
||||
//===-- HexagonTargetObjectFile.cpp - Hexagon asm properties --------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===-- HexagonTargetAsmInfo.h - Hexagon asm properties ---------*- C++ -*--==//
|
||||
//===-- HexagonTargetAsmInfo.h - Hexagon asm properties --------*- C++ -*--===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//==-- HexagonVarargsCallingConvention.h - Calling Conventions ---*- C++ -*-==//
|
||||
//===-- HexagonVarargsCallingConvention.h - Calling Conventions -*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===-- HexagonBaseInfo.h - Top level definitions for Hexagon -------------===//
|
||||
//===-- HexagonBaseInfo.h - Top level definitions for Hexagon --*- C++ -*--===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===-- HexagonMCAsmInfo.cpp - Hexagon asm properties -----------*- C++ -*-===//
|
||||
//===-- HexagonMCAsmInfo.cpp - Hexagon asm properties ---------------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue